參數(shù)資料
型號： AK61584
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:55; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-35 RoHS Compliant: No
中文描述： 雙低功耗的T1/E1線路接口
文件頁數(shù)： 11/38頁
文件大?。?/td> 364K
代理商： AK61584
ASAHI KASEI
[AK61584]
0185-E-00
98/04
-11-
OPERATING OPTIONS
The following are the major operating options which
are supported by the AK61584:
Control
Control of the AK61584 is via either
host mode
(seri-
al port) or
hardware mode
(individual control lines).
Hardware mode offers significantly fewer program-
mability options than the host mode.
T1/E1
The AK61584 supports T1 short-haul (DSX-1), and
E1 operation. The configuration pins (CON <0:2>)
and register bits control transmitted pulse shapes,
transmitter source impedance, and receiver slicing
level. Both channels must be operated at the same
rate (both T1 or both E1).
The pulse shapes are fully pre-defined by circuitry in
the AK61584, and are fully compliant with appropri-
ate standards when used with our application guideli-
nes in standard installations.
The transmitter impedance changes with the line
length options in order to match the impedance of the
load (75-ohm for E1 coax, 100-ohm for T1, 120- ohm
for E1 Shielded twisted pair).
The
receiver
slicing level is set at 65% for DSX-1
short-haul, and at 50% for all other applications.
Line Codes
The AK61584 supports a
transparent mode
where
the line code is encoded and decode by an external
T1/E1 framing device. Alternatively, a
coder mode
can be selected. In coder mode, an internal
B8ZS/AMI/HDB3 coder can be used on those sys-
tems which don't need T1/E1
framers (typically
high-speed multiplexers). In host mode, the choice of
transmit encoder is independent of the choice of re-
ceiver decoder.
Reference Clock
The AK61584 requires a T1 or E1 reference clock.
This clock can be either a 1-X clock (i.e.,1.544 MHz
or 2.048MHz). or can be a 8-X clock (i.e., 12.352
MHz or 16.384 MHz). In systems which want soft-
ware selection of data rate, the
1
-
X clock option is
typically chosen, and the reference clock is tied to the
transmit clock. In systems with a jittered transmit
clock, an external oscillator should drive the reference
clock input, and a 8-X rate can be used to minimize
the physical size of the oscillator. In either case, any
jitter present on the reference clock will not be filtered
by the jitter attenuator, and the reference clock should
have 100 ppm or better frequency accuracy.
Power Down
Either one of the two line interfaces may be indepen-
dently powered down.
Jitter Attenuator
The jitter attenuator may be placed in the receiver
path, the transmit path or bypassed entirely.
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