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參數(shù)資料
| 型號： | AK61584 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:55; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-35 RoHS Compliant: No |
| 中文描述： | 雙低功耗的T1/E1線路接口 |
| 文件頁數(shù)： | 20/38頁 |
| 文件大小： | 364K |
| 代理商： | AK61584 |
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ASAHI KASEI
[AK61584]
0185-E-00
98/04
-20-
Definition
Reset
Value
Register
Address
h10
b0010
Bit Name
1
0
Channel 1 Mask
7
6
5
4
3
2
1
0
Mask LOS1
Mask Latched-
LOS1
Mask AIS1
Mask Latched-
AIS1
Mask Latched-
BPV1
Mask Latched
-Overflow1
reserved
Mask
Interrupt1
Channel 2 Mask
Mask status bit 7
Mask status bit 6
Mask status bit 5
Mask status bit 4
Mask status bit 3
Mask status bit 2
Mask status bit 0 &
Interrupt pin
Enable status bit 7
Enable status bit 6
Enable status bit 5
Enable status bit 4
Enable status bit 3
Enable status bit 2
Enable status bit 0 &
Interrupt pin
0
0
0
0
0
0
0
0
h11
b0011
7
6
5
4
3
2
1
0
Mask LOS2
Mask Latched-
LOS2
Mask AIS2
Mask Latched-
AIS2
Mask Latched-
BPV2
Mask Latched
-Overflow2
reserved
Mask
Interrupt2
Mask status bit 7
Mask status bit 6
Mask status bit 5
Mask status bit 4
Mask status bit 3
Mask status bit 2
Mask status bit 0 &
Interrupt pin
Enable status bit 7
Enable status bit 6
Enable status bit 5
Enable status bit 4
Enable status bit 3
Enable status bit 2
Enable status bit 0 &
Interrupt pin
0
0
0
0
0
0
0
0
Note)Mask LOS and Mask Latched-LOS need to controlled simultaneously, and Mask AIS and Mask
Latched-AIS also.
Table 5(b). Mask Registers
Mask Registers Description
Writing a “1” to a bit of the mask register forces the corre-
sponding bit of the status register to stay fixed at “0”.
Control A Registers Description
Each bit in the control register is defined below.
AMI-R: Writing a “0”enables the B8ZS or HDB3
decoder in the receiver path. B8ZS vs. HDB3 se-
lection is determined by the CON<0:2> bits. Writing
a “1” enables the AMI decoder.
AMI-T: Writing a “0” enables the B8ZS or HDB3
encoder in the transmit path. B8ZS vs. HDB3 se-
lection is determined by the CON<0:2> bits. Writing
a “1” enables the AMI encoder.
CLKE: When CLKE is set to “1”. RPOS and
RNEG are valid on the falling edge of RCLK.
When CLKE is set to “0”, RPOS and RNEG are
valid on the rising edge of RCLK. This bit con-
trols the RPOS/RNEG polarity for both host
modes. The CLKE pin provides the same function-
ality for the hardware mode.
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