參數(shù)資料
型號: ADV7324
廠商: Analog Devices, Inc.
英文描述: Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
中文描述: 多格式視頻編碼器216兆赫六噪聲整形的14位DAC
文件頁數(shù): 78/92頁
文件大?。?/td> 992K
代理商: ADV7324
ADV7324
MODE 1—MASTER OPTION
(TIMING REGISTER 0 TR0 = X X X X X 0 1 1)
In this mode, the ADV7324 can generate horizontal sync and
odd/even field signals. When HSYNC is low, a transition of the
field input indicates a new frame, i.e., vertical retrace. The
BLANK signal is optional. When the BLANK input is disabled,
ADV7324 automatically blanks all normally blank lines as per
CCIR-624. Pixel data is latched on the rising clock edge
following the timing signal transitions. HSYNC, BLANK, and
FIELD are output on S_HSYNC, S_BLANK, and S_VSYNC,
respectively.
Rev. 0 | Page 78 of 92
622
623
624
625
21
22
23
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
FIELD
DISPLAY
309
310
311
312
313
314
315
316
317
318
319
334
335
336
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
DISPLAY
320
FIELD
5
7
6
4
3
2
1
HSYNC
BLANK
HSYNC
BLANK
0
Figure 113. SD Slave Mode 1 (PAL)
FIELD
PIXEL
DATA
PAL = 12
×
CLOCK/2
NTSC = 16
×
CLOCK/2
Cb
Y
Cr
Y
HSYNC
BLANK
PAL = 132
×
CLOCK/2
NTSC = 122
×
CLOCK/2
0
Figure 114. SD Timing Mode 1—Odd/Even Field Transitions Master/Slave
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