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參數(shù)資料
| 型號： | ADV7324 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | 多格式視頻編碼器216兆赫六噪聲整形的14位DAC |
| 文件頁數(shù)： | 61/92頁 |
| 文件大?。?/td> | 992K |
| 代理商： | ADV7324 |
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ADV7324
HSYNC/VSYNC OUTPUT CONTROL
The ADV7324 has the ability to accept either embedded time codes in the input data or external Hsync and Vsync signals on
P_HSYNC/P_VSYNC, outputting the respective signals on the P_HSYNC and P_VSYNC pins.
Rev. 0 | Page 61 of 92
Table 36. Hsync Output Control
1
HD/ED
2
Slave Mode
(0x10, Bit 2)
x
x
HD/ED
Sync Output
Enable
(0x02, Bit 7)
0
0
SD
Sync Output
Enable
(0x02, Bit 6)
0
1
I2C_Hsync_gen_sel
(0x14, Bit 1)
x
x
Signal on S_HSYNC Pin
Tristate
Pipelined SD Hsync
Duration
–
See Appendix 5—SD
Timing Modes
As per Hsync timing
External Hsync &
Vsync /Field
Mode
EAV/SAV Mode
1
x
0
External pipelined
HD/ED Hsync
1
x
0
Pipelined HD/ED Hsync based
on AV Code H bit
Pipelined HD/ED Hsync based
on horizontal counter
Same as line blanking
interval
Same as embedded
Hsync
x
1
x
1
______________________________
1
In all HD/ED standards where there is an Hsync o/p, the start of the Hsync pulse is aligned with the falling edge of the embedded Hsync in the output video.
2
ED = enhanced definition.
Table 37. Vsync Output Control
1
HD/ED
Sync Output
Enable
(0x02, Bit 7)
(0x02, Bit 6)
(0x14, Bit 2)
x
0
0
x
x
0
1
x
HD/ED
2
Slave Mode
(0x10, Bit 2)
SD
Sync Output
Enable
I2C_Vsync_gen_sel
Video Standard
x
Interlaced
Signal on
S_VSYNC Pin
Tristate
Pipelined SD
Vsync/ field
External pipelined
HD/ED Vsync or
field signal
External pipelined
field signal based
on AV Code F bit
Pipelined Vsync
based on AV
Code V bit
External pipelined
HD/ED Vsync
based on vertical
counter
External pipelined
HD/ED Vsync
based on vertical
counter
Duration
-
See Appendix 5—
SD Timing Modes
As per external
Vsync or field signal
External Hysnc
& Vsync/Field
Mode
EAV/SAV Mode
1
x
0
x
1
x
0
All HD interlace
standards
Field
EAV/SAV Mode
1
x
0
All HD/ED
progressive
standards
All HD/ED stan-
dards except 525p
Vertical blanking
interval
x
1
x
1
Aligned with
serration lines
x
1
x
1
525p
Vertical blanking
interval
1
In all HD/ED standards where there is an Hsync o/p, the start of the Hsync pulse is aligned with the falling edge of the embedded Hsync in the output video.
2
ED = enhanced definition = progressive scan 525p or 625p.
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