- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374047 > ADV7324 (Analog Devices, Inc.) Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs PDF資料下載
參數(shù)資料
| 型號： | ADV7324 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | 多格式視頻編碼器216兆赫六噪聲整形的14位DAC |
| 文件頁數(shù)： | 38/92頁 |
| 文件大?。?/td> | 992K |
| 代理商： | ADV7324 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當(dāng)前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
ADV7324
INPUT CONFIGURATION
When 10-bit input data is applied, the following bits must be set
to 1:
Rev. 0 | Page 38 of 92
Address 0x13, Bit 2 (HD 10-bit enable)
Address 0x48, Bit 4 (SD 10-bit enable)
Note that the ADV7324 defaults to simultaneous SD and PS
upon power-up (Address[0x01]: Input Mode = 011).
SD ONLY
Address[0x01]: Input Mode = 000
In 8-/10-bit input mode, multiplexed data is input on Pin S9 to
Pin S0 (or Pin Y9 to Pin Y0, depending on Register Address 0x01,
Bit 7), with S0 being the LSB in 10-bit input mode (see Table 21).
Input standards supported are ITU-R BT.601/656. In 16-/20-bit
input mode, the Y pixel data is input on Pin S9 to Pin S2, and
CrCb data is input on Pin Y9 to Pin Y2 (see Table 21).
16-/20-Bit Mode Operation
When Register 0x01, Bit 7 = 0, CrCb data is input on the Y bus,
and Y data is input on the S bus. When Register 0x01, Bit 7 = 1,
CrCb data is input on the C bus, and Y data is input on Y bus.
The 27 MHz clock input must be input on Pin CLKIN_A. Input
sync signals are input on the S_VSYNC, S_HSYNC, and
S_BLANK pins.
Table 21. SD 8-/10-Bit and 16-/20-Bit Configurations
Parameter
8-/10-Bit Mode
Register 0x01, Bit 7 = 0
Y Bus
S Bus
656/601, YCrCb
C Bus
Register 0x01, Bit 7 = 1
Y Bus
656/601, YCrCb
S Bus
C Bus
Configuration
16-/20-Bit Mode
CrCb
Y
Y
CrCb
MPEG2
DECODER
CLKIN_A
S[9:0] OR Y[9:0]*
27MHz
3
10
YCrCb
ADV7324
*SELECTED BY ADDRESS 0x01, BIT 7
0
S_VSYNC,
S_HSYNC,
S_BLANK
Figure 48. SD Only Input Mode
PS ONLY OR HDTV ONLY
Address[0x01]: Input Mode = 001 or 010, Respectively
YCrCb PS, HDTV, or any other HD YCrCb data can be input in
4:2:2 or 4:4:4. In 4:2:2 input format, the Y data is input on Pin Y9
to Pin Y0, and the CrCb data is input on Pin C9 to Pin C0. In
4:4:4 input mode, Y data is input on Pin Y9 to Pin Y0, Cb data is
input on Pin C9 to Pin C0, and Cr data is input on Pin S9 to
Pin S0. If the YCrCb data does not conform to SMPTE 293M
(525p), ITU-R BT.1358M (625p), SMPTE 274M (1080i),
SMPTE 296M (720p), SMPTE 240M (1035i), or BTA-T1004/1362,
the async timing mode must be used. RGB data can only be
input in 4:4:4 format in PS or HDTV input modes when HD RGB
input is enabled. G data is input on Pin Y9 to Pin Y0, R data is
input on Pin S9 to Pin S0, and B data is input on Pin C9 to Pin C0.
The clock signal must be input on Pin CLKIN_A.
MPEG2
DECODER
CLKIN_A
C[9:0]
10
Cb
S[9:0]
Y[9:0]
INTERLACED TO
PS
YCrCb
10
Cr
10
Y
3
27MHz
ADV7324
0
P_VSYNC,
P_HSYNC,
P_BLANK
Figure 49. PS Input Mode
SIMULTANEOUS SD/PS OR SD/HDTV
Address[0x01]: Input Mode 011 (SD 10-Bit, PS 20-Bit), Input
Mode 101 (SD and HD, SD Oversampled), or Input Mode
110 (SD and HD, HD Oversampled)
YCrCb PS and HD data must be input in 4:2:2 format. In 4:2:2
input format, the HD Y data is input on Pin Y9 to Pin Y0, and
the HD CrCb data is input on Pin C9 to Pin C0. If PS 4:2:2 data is
inter-leaved onto a single 10-bit bus, Pin Y9 to Pin Y0 are used
for the input port. The input data is input at 27 MHz, with the
data being clocked upon the rising and falling edges of the input
clock. The input mode register at Address 0x01 is set accordingly.
If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE 296M
(720p), SMPTE 240M (1035i), or BTA-T1004, the async timing
mode must be used.
The 8- or 10-bit SD data must be compliant with ITU-R
BT.601/656 in 4:2:2 format. SD data is input on Pin S9 to Pin S0,
with S0 being the LSB. Using 8-bit input format, the data is
input on Pin S9 to Pin S2. The clock input for SD must be input
on CLKIN_A, and the clock input for HD must be input on
CLKIN_B. Synchronization signals are optional. SD syncs are
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7324KSTZ | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| ADV7340 | Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
| ADV7340BSTZ | Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
| ADV7340EBZ | Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
| ADV7341 | Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7324KSTZ | 制造商:Analog Devices 功能描述:Video Encoder 64-Pin LQFP |
| ADV7330 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat 11-Bit Triple DAC Video Encoder |
| ADV73305502 | 制造商:LG Corporation 功能描述:FRAME ASSEMBLY |
| ADV73306701 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73306702 | 制造商:LG Corporation 功能描述:Frame Assembly |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。