參數(shù)資料
型號(hào)： ADV7324
廠商： Analog Devices, Inc.
英文描述： Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
中文描述： 多格式視頻編碼器216兆赫六噪聲整形的14位DAC
文件頁(yè)數(shù)： 39/92頁(yè)
文件大?。?/td> 992K
代理商： ADV7324
ADV7324
input on Pin S_VSYNC, Pin S_HSYNC, and Pin S_BLANK.
HD syncs are input on Pin P_VSYNC, Pin P_HSYNC, and
Pin P_BLANK.
Rev. 0 | Page 39 of 92
CLKIN_A
CLKIN_B
MPEG2
DECODER
3
27MHz
10
YCrCb
INTERLACED TO
PS
10
CrCb
10
Y
3
27MHz
S[9:0]
C[9:0]
Y[9:0]
P_VSYNC,
P_HSYNC,
P_BLANK
ADV7324
0
S_VSYNC,
S_HSYNC,
S_BLANK
Figure 50. Simultaneous SD and PS Input
CLKIN_A
CLKIN_B
SDTV
DECODER
3
27MHz
10
YCrCb
10
CrCb
10
Y
3
74.25MHz
1080i
OR
720p
OR
1035i
S[9:0]
C[9:0]
Y[9:0]
P_VSYNC,
P_HSYNC,
P_BLANK
ADV7324
HDTV
DECODER
0
S_VSYNC,
S_HSYNC,
S_BLANK
Figure 51. Simultaneous SD and HD Input
In simultaneous SD/HD input mode, if the two clock phases
differ by less than 9.25 ns or by more than 27.75 ns, the clock
align bit [Address 0x01, Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
clock align bit must be set because the phase difference between
both inputs is less than 9.25 ns.
CLKIN_A
CLKIN_B
0
t
DELAY
<
9.25ns OR
t
DELAY
>
27.75ns
Figure 52. Clock Phase with Two Input Clocks
PS AT 27 MHZ (DUAL EDGE)
OR 54 MHZ
Address[0x01]: Input Mode 100 or 111, Respectively
YCrCb PS data can be input at 27 MHz or 54 MHz. The input
data is interleaved onto a single 8-/10-bit bus and is input on
Pin Y9 to Pin Y0. When a 27 MHz clock is supplied, the data is
clocked upon the rising and falling edges of the input clock, and
the clock edge bit [Address 0x01, Bit 1] must be set accordingly.
Table 22 provides an overview of all possible input configurations.
Figure 53, Figure 54, and Figure 55 show the possible conditions:
Cb data on the rising edge, and Y data on the rising edge.
3FF
00
00
XY
Y0
Y1
Cr0
CLKIN_B
CLOCK EDGE ADDRESS 0x00, BIT 1, SHOULD BE SET TO 0 IN THIS CASE.
Y9–Y0
Cb0
0
Figure 53. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
3FF
00
00
XY
Cb0
Cr0
Y1
CLKIN_B
Y9–Y0
Y0
CLOCK EDGE ADDRESS 0x00, BIT 1, SHOULD BE SET TO 1 IN THIS CASE.
0
Figure 54. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
PIXEL INPUT
DATA
3FF
00
00
XY
Cb0
Y0
Y1
Cr0
CLKIN_B
WITH A 54MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.
0
Figure 55. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
MPEG2
DECODER
CLKIN_A
Y[9:0]
INTERLACED
TO PS
YCrCb
10
3
27MHz OR 54MHz
YCrCb
ADV7324
P_VSYNC,
P_HSYNC,
P_BLANK
0
Figure 56. 10-Bit PS at 27 MHz or 54 MHz
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