參數(shù)資料
型號(hào)： ADV7324
廠商： Analog Devices, Inc.
英文描述： Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
中文描述： 多格式視頻編碼器216兆赫六噪聲整形的14位DAC
文件頁(yè)數(shù)： 43/92頁(yè)
文件大?。?/td> 992K
代理商： ADV7324
ADV7324
HD TIMING RESET
A timing reset is achieved by toggling the HD timing reset control
bit [Subaddress 0x14, Bit 0] from 0 to 1. In this state, the horizontal
and vertical counters remain reset. When this bit is set back to 0,
the internal counters resume counting.
Rev. 0 | Page 43 of 92
The minimum time the pin must be held high is one clock
cycle; otherwise, this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.
SD REAL-TIME CONTROL, SUBCARRIER RESET,
AND TIMING RESET
[Subaddress 0x44, Bit 2 and Bit 1]
Together with the RTC_SCR_TR pin and SD Mode Register 3
[Address 0x44, Bit 1 and Bit 2], the ADV7324 can be used in
(a) timing reset mode, (b) subcarrier phase reset mode, or
(c) RTC mode.
a.
A timing reset is achieved after a low-to-high
transition on the RTC_SCR_TR pin (Pin 31). In this
state, the horizontal and vertical counters remain
reset. Upon releasing this pin (set to low), the internal
counters resume counting, starting with Field 1, and
the subcarrier phase is reset.
The minimum time the pin must be held high is one
clock cycle; otherwise, this reset signal might not be
recognized. This timing reset applies to the SD timing
counters only.
b.
In subcarrier phase reset, a low-to-high transition on
the RTC_SCR_TR pin (Pin 31) resets the subcarrier
phase to 0 on the field following the subcarrier phase
reset when the SD RTC/TR/SCR control bits at
Address 0x44 are set to 01.
This reset signal must be held high for a minimum of
one clock cycle.
Because the field counter is not reset, it is
recommended that the reset signal is applied in Field 7
(PAL) or Field 3 (NTSC). The reset of the phase will
then occur on the next field, i.e., Field 1, lined up
correctly with the internal counters. The field count
register at Address 0x7B can be used to identify the
number of active fields.
c.
In RTC mode, the ADV7324 can be used to lock to an
external video source. The real-time control mode
allows the ADV7324 to automatically alter the
subcarrier frequency to compensate for line length
variations. When the part is connected to a device,
such as an ADV7402A video decoder (see Figure 61),
that outputs a digital data stream in RTC format, it
automatically changes to the compensated subcarrier
frequency on a line-by-line basis. This digital data
stream is 67 bits wide, and the subcarrier is contained
in Bit 0 to Bit 21. Each bit is two clock cycles long.
Write 0x00 into all four subcarrier frequency registers
when this mode is used.
DISPLAY
NO TIMING RESET APPLIED
TIMING RESET APPLIED
START OF FIELD 4 OR 8
F
SC
PHASE = FIELD 4 OR 8
F
SC
PHASE = FIELD 1
TIMING RESET PULSE
307
310
307
1
2
3
4
5
6
7
21
313
320
DISPLAY
START OF FIELD 1
0
Figure 59. Timing Reset Timing Diagram
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ADV7324KSTZ Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
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