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參數(shù)資料
| 型號： | ADV7324 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | 多格式視頻編碼器216兆赫六噪聲整形的14位DAC |
| 文件頁數(shù)： | 42/92頁 |
| 文件大?。?/td> | 992K |
| 代理商： | ADV7324 |
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ADV7324
HD ASYNC TIMING MODE
[Subaddress 0x10, Bits 3 and 2]
Rev. 0 | Page 42 of 92
For any input data that does not conform to the standards
selectable in input mode (Subaddress 0x10), asynchronous
timing mode can be used to interface to the ADV7324. Timing
control signals for HSYNC, VSYNC, and BLANK must be
programmed by the user. Macrovision and programmable
oversampling rates are not available in async timing mode.
Table 26. Async Timing Mode Truth Table
P_HSYNC P_VSYNC P_BLANK
1
1
→
0
0
0 or 1
0
0
→
1
0 or 1
0
→
1
0 or 1
0
1
0 or 1
0
→
1
1
0 or 1
1
→
0
In async mode, the PLL must be turned off [Subaddress 0x00,
Bit 1 = 1]. Register 0x10 should be programmed to 0x01.
Figure 57 and Figure 58 show examples of how to program the
ADV7324 to accept an HD standard other than SMPTE 293M,
SMPTE 274M, SMPTE 296M, or ITU-R BT.1358.
Follow the specifications in Table 26 when programming the
control signals in async timing mode. For standards that do not
require a trisync level, P_BLANK must be tied low at all times.
Reference
50% point of falling edge of trilevel horizontal sync signal
25% point of rising edge of trilevel horizontal sync signal
50% point of falling edge of trilevel horizontal sync signal
50% start of active video
50% end of active video
Reference in Figure 57
and Figure 58
a
b
c
d
e
1
When async timing mode is enabled, P_BLANK, Pin 25, becomes an active high input. P_BLANK is set to active low using Address 0x10, Bit 6.
CLK
ACTIVE VIDEO
PROGRAMMABLE
INPUT TIMING
ANALOG
OUTPUT
81
66
66
243
1920
HORIZONTAL SYNC
e
d
c
b
a
SET ADDRESS 0x14,
BIT 3 = 1
0
P_HSYNC
P_VSYNC
P_BLANK
Figure 57. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility
ACTIVE VIDEO
0
1
HORIZONTAL SYNC
e
d
c
b
a
CLK
SET ADDRESS 0x14
BIT 3 = 1
ANALOG OUTPUT
0
P_VSYNC
P_BLANK
P_HSYNC
Figure 58. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal
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