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| 型號(hào)： | ADUC834BCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/80頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 62KB（62K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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REV. A
ADuC834
–15–
Table II. PCON SFR Bit Designations
Bit
Name
Description
7SMOD
Double UART Baud Rate
6
SERIPD
SPI Power-Down Interrupt Enable
5
INT0PD
INT0 Power-Down Interrupt Enable
4
ALEOFF
Disable ALE Output
3
GF1
General-Purpose Flag Bit
2
GF0
General-Purpose Flag Bit
1PD
Power-Down Mode Enable
0
IDL
Idle Mode Enable
ADuC834 CONFIGURATION SFR (CFG834)
The CFG834 SFR contains the necessary bits to configure the
internal XRAM and the extended SP. By default it configures
the user into 8051 mode, i.e., extended SP is disabled, internal
XRAM is disabled.
SFR Address
AFH
Power-On Default Value
00H
Bit Addressable
No
Table III. CFG834 SFR Bit Designations
Bit
Name
Description
7
EXSP
Extended SP Enable. If this bit is set, the
stack will roll over from SPH/SP = 00FFH
to 0100H. If this bit is clear, the SPH SFR
will be disabled and the stack will roll
over from SP = FFH to SP = 00H
6
–––
Reserved for Future Use
5
–––
Reserved for Future Use
4
–––
Reserved for Future Use
3
–––
Reserved for Future Use
2
–––
Reserved for Future Use
1
–––
Reserved for Future Use
0
XRAMEN
XRAM Enable Bit. If this bit is set, the
internal XRAM will be mapped into the
lower 2 Kbytes of the external address
space. If this bit is clear, the internal
XRAM will not be accessible and the
external data memory will be mapped
into the lower 2 Kbytes of external data
memory. (See Figure 3.)
Stack Pointer (SP and SPH)
The SP SFR is the stack pointer and is used to hold an internal
RAM address that is called the ‘top of the stack.’ The SP Register
is incremented before data is stored during PUSH and CALL
executions. While the Stack may reside anywhere in on-chip
RAM, the SP Register is initialized to 07H after a reset. This
causes the stack to begin at location 08H.
As mentioned earlier, the ADuC834 offers an extended 11-bit
stack pointer. The three extra bits to make up the 11-bit stack
pointer are the 3 LSBs of the SPH byte located at B7H.
Program Status Word (PSW)
The PSW SFR contains several bits reflecting the current status
of the CPU as detailed in Table I.
SFR Address
D0H
Power-On Default Value
00H
Bit Addressable
Yes
Table I. PSW SFR Bit Designations
Bit
Name
Description
7CYCarry Flag
6ACAuxiliary Carry Flag
5F0General-Purpose Flag
4
RS1
Register Bank Select Bits
3
RS0
RS1
RS0
Selected Bank
000
011
102
113
2OVOverflow Flag
1F1General-Purpose Flag
0P
Parity Bit
Power Control SFR (PCON)
The PCON SFR contains bits for power-saving options and
general-purpose status flags as shown in Table II.
The TIC (wake-up/RTC timer) can be used to accurately wake up
the ADuC834 from power-down at regular intervals. To use the
TIC to wake up the ADuC834 from power-down, the OSC_PD
bit in the PLLCON SFR must be clear and the TIC must be
enabled.
SFR Address
87H
Power-On Default Value
00H
Bit Addressable
No
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