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參數(shù)資料
| 型號： | ADUC834BCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 52/80頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 標準包裝： | 2,500 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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REV. A
–56–
ADuC834
T2CON
Timer/Counter 2 Control Register
SFR Address
C8H
Power-On Default Value
00H
Bit Addressable
Yes
Table XXIX. T2CON SFR Bit Designations
Bit
Name
Description
7
TF2
Timer 2 Overflow Flag.
Set by hardware on a Timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1.
Cleared by user software.
6
EXF2
Timer 2 External Flag.
Set by hardware when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1.
Cleared by user software.
5
RCLK
Receive Clock Enable Bit.
Set by user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3.
Cleared by user to enable Timer 1 overflow to be used for the receive clock.
4
TCLK
Transmit Clock Enable Bit.
Set by user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3.
Cleared by user to enable Timer 1 overflow to be used for the transmit clock.
3
EXEN2
Timer 2 External Enable Flag.
Set by user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2
is not being used to clock the serial port.
Cleared by user for Timer 2 to ignore events at T2EX.
2
TR2
Timer 2 Start/Stop Control Bit.
Set by user to start Timer 2.
Cleared by user to stop Timer 2.
1
CNT2
Timer 2 Timer or Counter Function Select Bit.
Set by user to select counter function (input from external T2 Pin).
Cleared by user to select timer function (input from on-chip core clock).
0
CAP2
Timer 2 Capture/Reload Select Bit.
Set by user to enable captures on negative transitions at T2EX if EXEN2 = 1.
Cleared by user to enable auto reloads with Timer 2 overflows or negative transitions at T2EX when
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to
autoreload on Timer 2 overflow.
Timer/Counter 2 Data Registers
Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and timer
capture/reload registers.
TH2 and TL2
Timer 2, data high byte and low byte.
SFR Address = CDH, CCH, respectively.
RCAP2H and RCAP2L
Timer 2, Capture/Reload byte and low byte.
SFR Address = CBH, CAH, respectively.
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