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參數(shù)資料
| 型號： | ADUC834BCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 41/80頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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REV. A
–46–
ADuC834
Three SFRs are used to control the I
2C interface. These are described below.
I2CCON
I
2C Control Register
SFR Address
E8H
Power-On Default Value
00H
Bit Addressable
Yes
Table XXII. I2CCON SFR Bit Designations
Bit
Name
Description
7
MDO
I
2C Software Master Data Output Bit (Master Mode Only).
This data bit is used to implement a master I
2C transmitter interface in software. Data written to this
bit will be outputted on the SDATA pin if the data output enable (MDE) bit is set.
6
MDE
I
2C Software Master Data Output Enable Bit (Master Mode Only).
Set by the user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable SDATA pin as an input (Rx).
5
MCO
I
2C Software Master Clock Output Bit (Master Mode Only).
This data bit is used to implement a master I
2C transmitter interface in software. Data written to
this bit will be outputted on the SCLOCK pin.
4
MDI
I
2C Software Master Data Input Bit (Master Mode Only).
This data bit is used to implement a master I
2C receiver interface in software. Data on the SDATA
pin is latched into this bit on SCLOCK if the data output enable (MDE) bit is 0.
3
I2CM
I
2C Master/Slave Mode Bit.
Set by the user to enable I
2C software master mode.
Cleared by user to enable I
2C hardware slave mode.
2
I2CRS
I
2C Reset Bit (Slave Mode Only).
Set by the user to reset the I
2C interface.
Cleared by user code for normal I
2C operation.
1I2CTX
I
2C Direction Transfer Bit (Slave Mode Only).
Set by the MicroConverter if the interface is transmitting.
Cleared by the MicroConverter if the interface is receiving.
0
I2CI
I
2C Interrupt Bit (Slave Mode Only).
Set by the MicroConverter after a byte has been transmitted or received.
Cleared automatically when the user code reads the I2CDAT SFR (see I2CDAT below).
I2CADD
I
2C Address Register
Function
Holds the I
2C peripheral address for the part. It may be overwritten by the user code. Application Note uC001
at www.analog.com/microconverter describes the format of the I
2C standard 7-bit address in detail.
SFR Address
9BH
Power-On Default Value
55H
Bit Addressable
No
I2CDAT
I
2C Data Register
Function
The I2CDAT SFR is written by the user to transmit data over the I
2C interface or read by user code to
read data just received by the I
2C interface. Accessing I2CDAT automatically clears any pending I2C
interrupt and the I2CI bit in the I2CCON SFR. User software should only access I2CDAT once per
interrupt cycle.
SFR Address
9AH
Power-On Default Value
00H
Bit Addressable
No
* Purchase of licensed I
2C components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I
2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
I
2C SERIAL INTERFACE
The ADuC834 supports a fully licensed
* I2C serial interface. The
I
2C interface is implemented as a full hardware slave and software
master. SDATA (Pin 27) is the data I/O pin and SCLOCK
(Pin 26) is the serial clock. These two pins are shared with the
MOSI and SCLOCK pins of the on-chip SPI interface. Therefore
the user can only enable one or the other interface at any given
time (see SPE in Table XXI). Application Note uC001 describes
the operation of this interface as implemented and is available from
the MicroConverter website at www.analog.com/microconverter.
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