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參數(shù)資料
| 型號： | ADUC834BCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/80頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 標準包裝： | 2,500 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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REV. A
ADuC834
–45–
SPIDAT
SPI Data Register
Function
The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user
code to read data just received by the SPI interface.
SFR Address
F7H
Power-On Default Value
00H
Bit Addressable
No
Using the SPI Interface
Depending on the configuration of the bits in the SPICON SFR
shown in Table XXI, the ADuC834 SPI interface will transmit
or receive data in a number of possible modes. Figure 34 shows
all possible ADuC834 SPI configurations and the timing rela-
tionships and synchronization between the signals involved.
Also shown in this figure is the SPI interrupt bit (ISPI) and how
it is triggered at the end of each byte-wide communication.
SCLOCK
(CPOL = 1)
SCLOCK
(CPOL = 0)
(CPHA = 1)
(CPHA = 0)
SAMPLE INPUT
ISPI FLAG
DATA OUTPUT
ISPI FLAG
SAMPLE INPUT
DATA OUTPUT
?
MSB BIT 6 BIT 5
?
BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
SS
Figure 34. SPI Timing, All Modes
SPI Interface—Master Mode
In Master Mode, the SCLOCK pin is always an output and
generates a burst of eight clocks whenever user code writes to
the SPIDAT Register. The SCLOCK bit rate is determined by
SPR0 and SPR1 in SPICON. It should also be noted that the
SS Pin is not used in Master mode. If the ADuC834 needs to
assert the
SS Pin on an external slave device, a port digital output
pin should be used.
In Master Mode, a byte transmission or reception is initiated by
a write to SPIDAT. Eight clock periods are generated via the
SCLOCK pin and the SPIDAT byte being transmitted via
MOSI. With each SCLOCK period, a data bit is also sampled
via MISO. After eight clocks, the transmitted byte will have
been completely transmitted and the input byte will be waiting
in the input shift register. The ISPI flag will be set automatically
and an interrupt will occur if enabled. The value in the shift
register will be latched into SPIDAT.
SPI Interface—Slave Mode
In Slave Mode, the SCLOCK is an input. The
SS pin must also
be driven low externally during the byte communication. Trans-
mission is also initiated by a write to SPIDAT. In Slave Mode,
a data bit is transmitted via MISO and a data bit is received via
MOSI through each input SCLOCK period. After eight clocks,
the transmitted byte will have been completely transmitted and
the input byte will be waiting in the input shift register. The ISPI
flag will be set automatically and an interrupt will occur if enabled.
The value in the shift register will be latched into SPIDAT
only when the transmission/reception of a byte has been com-
pleted. The end of transmission occurs after the eighth clock has
been received, if CPHA = 1 or when
SS returns high if CPHA = 0.
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