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| 型號(hào)： | ADUC834BCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 55/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 62KB（62K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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REV. A
ADuC834
–59–
CORE
CLK*
2
T2
PIN
TR2
CONTROL
TL2
(8 BITS)
TH2
(8 BITS)
RELOAD
EXEN2
CONTROL
T2EX
PIN
TRANSITION
DETECTOR
EXF 2
TIMER 2
INTERRUPT
NOTE AVAILABILITY OF ADDITIONAL
EXTERNAL INTERRUPT
*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE "ON-CHIP PLL")
RCAP2L
RCAP2H
TIMER 2
OVERFLOW
2
16
RCLK
TCLK
RX
CLOCK
TX
CLOCK
0
1
0
SMOD
TIMER 1
OVERFLOW
C/
T2 = 0
C/
T2 = 1
OSC. FREQ. IS DIVIDED BY 2, NOT 12.
Figure 56. Timer 2, UART Baud Rates
BAUD RATE GENERATION USING TIMER 1 AND TIMER 2
Timer 1 Generated Baud Rates
When Timer 1 is used as the baud rate generator, the baud rates
in Modes 1 and 3 are determined by the Timer 1 overflow rate
and the value of SMOD as follows:
Modes 1
3
1
and
Baud Rate
Timer
Overflow Rate
SMOD
=
() × ()
232
The Timer 1 interrupt should be disabled in this application.
The timer itself can be configured for either timer or counter
operation, and in any of its three running modes. In the most
typical application, it is configured for timer operation, in the
Autoreload Mode (high nibble of TMOD = 0100 binary). In
that case, the baud rate is given by the formula:
Mode 1
3
1
and Mode
Baud Rate
f
TH
SMOD
CORE
=
×
()
2
32
12 256
A very low baud rate can also be achieved with Timer 1 by
leaving the Timer 1 interrupt enabled, configuring the timer to
run as a 16-bit timer (high nibble of TMOD = 0100 binary), and
using the Timer 1 interrupt to do a 16-bit software reload.
Table XXXI shows some commonly-used baud rates and how
they might be calculated from a core clock frequency of 1.5728
MHz and 12.58 MHz using Timer 1. Generally speaking, a 5%
error is tolerable using asynchronous (start/stop) communications.
Table XXXI. Commonly Used Baud Rates, Timer 1
Ideal
Core
SMOD
TH1-Reload
Actual
%
Baud
CLK
Value
Baud
Error
9600
12.58
1
–7 (F9H)
9362
2.5
1600
12.58
1
–27 (E5H)
1627
1.1
1200
12.58
1
–55 (C9H)
1192
0.7
1200
1.57
1
–7 (F9H)
1170
2.5
Timer 2 Generated Baud Rates
Baud rates can also be generated using Timer 2. Using Timer 2
is similar to using Timer 1 in that the timer must overflow 16
times before a bit is transmitted/received. Because Timer 2 has
a 16-bit Autoreload Mode, a wider range of baud rates is pos-
sible using Timer 2.
Mode 1
and Mode
Baud Rate
Timer
Overflow Rate
31 16
2
=
() × ()
Therefore when Timer 2 is used to generate baud rates, the
timer increments every two clock cycles and not every core
machine cycle as before. Thus, it increments six times faster
than Timer 1, and therefore baud rates six times faster are pos-
sible. Because Timer 2 has a 16-bit autoreload capability, very
low baud rates are still possible.
Timer 2 is selected as the baud rate generator by setting the
TCLK and/or RCLK in T2CON. The baud rates for transmit
and receive can be simultaneously different. Setting RCLK and/or
TCLK puts Timer 2 into its baud rate generator mode as shown
in Figure 56. In this case, the baud rate is given by the formula:
Mode 1
3
and Mode
Baud Rate
f
RCAP H L
CORE
=
×
()
32
65536
2
Table XXXII shows some commonly used baud rates and
how they might be calculated from a core clock frequency of
1.5728 MHz and 12.5829 MHz using Timer 2.
Table XXXII. Commonly Used Baud Rates, Timer 2
Ideal
Core
RCAP2H
RCAP2L
Actual
%
Baud
CLK
Value
Baud
Error
19200
12.58
–1 (FFH)
–20 (ECH)
19661
2.4
9600
12.58
–1 (FFH)
–41 (D7H)
9591
0.1
1600
12.58
–1 (FFH)
–164 (5CH) 2398
0.1
1200
12.58
–2 (FEH)
–72 (B8H)
1199
0.1
9600
1.57
–1 (FFH)
–5 (FBH)
9830
2.4
1600
1.57
–1 (FFH)
–20 (ECH)
1658
2.4
1200
1.57
–1 (FFH)
–41 (D7H)
1199
0.1
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