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| 型號： | ADUC834BCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 標準包裝： | 2,500 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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REV. A
–42–
ADuC834
Table XIX. WDCON SFR Bit Designations
Bit
Name
Description
7
PRE3
Watchdog Timer Prescale Bits.
6
PRE2
The Watchdog timeout period is given by the equation: tWD = (2
PRE
(2
9/f
PLL))
5
PRE1
(0
≤ PRE ≤ 7; fPLL = 32.768 kHz)
4
PRE0
PRE3
PRE2 PRE1
PRE0
Timeout Period (ms)
Action
00
15.6
Reset or Interrupt
00
01
31.2
Reset or Interrupt
00
10
62.5
Reset or Interrupt
00
11
125
Reset or Interrupt
01
00
250
Reset or Interrupt
01
500
Reset or Interrupt
01
10
1000
Reset or Interrupt
01
11
2000
Reset or Interrupt
10
00
0.0
Immediate Reset
PRE3–0 > 1001
Reserved
3
WDIR
Watchdog Interrupt Response Enable Bit. If this bit is set by the user, the watchdog will generate an
interrupt response instead of a system reset when the watchdog timeout period has expired. This
interrupt is not disabled by the CLR
EA instruction and it is also a fixed, high-priority interrupt. If the
watchdog is not being used to monitor the system, it can alternatively be used as a timer. The prescaler
is used to set the timeout period in which an interrupt will be generated.
(See also Note 1, Table XXXIX in the Interrupt System section.)
2
WDS
Watchdog Status Bit.
Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.
Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset.
1
WDE
Watchdog Enable Bit.
Set by user to enable the watchdog and clear its counters. If a 1 is not written to this bit within the
watchdog timeout period, the watchdog will generate a reset or interrupt, depending on WDIR.
Cleared under the following conditions, User writes 0, Watchdog Reset (WDIR = 0);
Hardware Reset; PSM Interrupt.
0
WDWR
Watchdog Write Enable Bit.
To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must
be set and the very next instruction must be a write instruction to the WDCON SFR. For example:
CLR
EA
; disable interrupts while writing
; to WDT
SETB
WDWR
; allow write to WDCON
MOV
WDCON, #72h
; enable WDT for 2.0s timeout
SETB
EA
; enable interrupts again (if rqd)
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset or
interrupt within a reasonable amount of time if the ADuC834
enters an erroneous state, possibly due to a programming error,
electrical noise, or RFI. The watchdog function can be disabled
by clearing the WDE (Watchdog Enable) bit in the Watchdog
Control (WDCON) SFR. When enabled; the watchdog circuit
will generate a system reset or interrupt (WDS) if the user program
fails to set the Watchdog (WDE) bit within a predetermined
amount of time (see PRE3–0 bits in WDCON). The watchdog
timer itself is a 16-bit counter that is clocked at 32.768 kHz. The
watchdog timeout interval can be adjusted via the PRE3–0 bits
in WDCON. Full control and status of the watchdog timer
function can be controlled via the Watchdog Timer Control SFR
(WDCON). The WDCON SFR can only be written by user
software if the double write sequence described in WDWR
below is initiated on every write access to the WDCON SFR.
WDCON
Watchdog Timer Control Register
SFR Address
C0H
Power-On Default Value
10H
Bit Addressable
Yes
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