參數資料
型號: ADUC834BCPZ-REEL
廠商: Analog Devices Inc
文件頁數: 20/80頁
文件大小: 0K
描述: IC MCU 62K FLASH ADC/DAC 56LFCSP
標準包裝: 2,500
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 12.58MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設備: POR,PSM,PWM,溫度傳感器,WDT
輸入/輸出數: 34
程序存儲器容量: 62KB(62K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.25 V
數據轉換器: A/D 3x16b,4x24b; D/A 1x12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
包裝: 帶卷 (TR)
REV. A
ADuC834
–27–
In operation, the analog signal sample is fed to the difference
amplifier along with the output of the feedback DAC. The
difference between these two signals is integrated and fed to the
comparator. The output of the comparator provides the input to
the feedback DAC so the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital
data that represents the analog input voltage is contained in the
duty cycle of the pulse train appearing at the output of the com-
parator. This duty cycle data can be recovered as a data-word
using a subsequent digital filter stage. The sampling frequency of
the modulator loop is many times higher than the bandwidth
of the input signal. The integrator in the modulator shapes the
quantization noise (which results from the analog-to-digital
conversion) so that the noise is pushed toward one-half of the
modulator frequency.
Digital Filter
The output of the
-
modulator feeds directly into the digital
filter. The digital filter then band-limits the response to a fre-
quency significantly lower than one-half of the modulator frequency.
In this manner, the 1-bit output of the comparator is translated
into a band-limited, low noise output from the ADuC834 ADCs.
The ADuC834 filter is a low-pass, Sinc
3 or (SIN x/x)3 filter
whose primary function is to remove the quantization noise
introduced at the modulator. The cutoff frequency and decimated
output data rate of the filter are programmable via the SF (Sinc
Filter) SFR as described in Table VIII.
Figure 11 shows the frequency response of the ADC channel at
the default SF word of 69 dec or 45H, yielding an overall output
update rate of just under 20 Hz.
It should be noted that this frequency response allows frequency
components higher than the ADC Nyquist frequency to pass
through the ADC, in some cases without significant attenuation.
These components may, therefore, be aliased and appear
in-band after the sampling process.
It should also be noted that rejection of mains-related frequency
components, i.e., 50 Hz and 60 Hz, is seen to be at a level of
>65 dB at 50 Hz and >100 dB at 60 Hz. This confirms the data
sheet specifications for 50 Hz/60 Hz Normal Mode Rejection
(NMR) at a 20 Hz update rate.
020
30
50
70
8090
100
110
FREQUENCY – Hz
GAIN
dB
0
–20
–40
–70
–80
–90
–100
–110
–120
10
40
60
–10
–30
–60
–50
Figure 11. Filter Response, SF = 69 dec
The response of the filter, however, will change with SF word as
can be seen in Figure 12, which shows >90 dB NMR at 50 Hz
and >70 dB NMR at 60 Hz when SF = 255 dec.
020
30
50
7080
90
110
FREQUENCY – Hz
GAIN
dB
0
–20
–40
–70
–80
–90
–100
–110
–120
10
40
60
–10
–30
–60
–50
Figure 12. Filter Response, SF = 255 dec
Figures 13 and 14 show the NMR for 50 Hz and 60 Hz across
the full range of SF word, i.e., SF = 13 dec to SF = 255 dec.
10
50
70
110
150 170 190 210
SF – Decimal
GAIN
dB
0
–20
–40
–70
–80
–90
–100
–110
–120
30
90
130
–10
–30
–60
–50
230 250
Figure 13. 50 Hz Normal Mode Rejection vs. SF
10
50
70
110
150 170 190 210
SF – Decimal
GAIN
dB
0
–20
–40
–70
–80
–90
–100
–110
–120
30
90
130
–10
–30
–60
–50
230 250
Figure 14. 60 Hz Normal Mode Rejection vs. SF
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