Note that Figure 22 represents a transfer function in 0-to-VDD mod" />
參數(shù)資料
型號: ADUC834BCPZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 29/80頁
文件大?。?/td> 0K
描述: IC MCU 62K FLASH ADC/DAC 56LFCSP
標準包裝: 2,500
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 12.58MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設備: POR,PSM,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 62KB(62K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x16b,4x24b; D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
包裝: 帶卷 (TR)
REV. A
ADuC834
–35–
Note that Figure 22 represents a transfer function in 0-to-VDD
mode only. In 0-to-VREF mode (with VREF < VDD), the lower
nonlinearity would be similar, but the upper portion of the
transfer function would follow the “ideal” line right to the end,
showing no signs of endpoint linearity errors.
VDD
VDD–50mV
VDD–100mV
100mV
50mV
0mV
000 Hex
FFF Hex
Figure 22. Endpoint Nonlinearities Due to Amplifier
Saturation
The endpoint nonlinearities conceptually illustrated in Figure 22
get worse as a function of output loading. Most of the ADuC834
data sheet specifications assume a 10 k
resistive load to
ground at the DAC output. As the output is forced to source or
sink more current, the nonlinear regions at the top or bottom
(respectively) of Figure 22 become larger. With larger current
demands, this can significantly limit output voltage swing.
Figures 23 and 24 illustrate this behavior. It should be noted
that the upper trace in each of these figures is only valid for an
output range selection of 0-to-AVDD. In 0-to-VREF mode, DAC
loading will not cause high-side voltage drops as long as the
reference voltage remains below the upper trace in the corre-
sponding figure. For example, if AVDD = 3 V and VREF = 2.5 V,
the high-side voltage will not be affected by loads less than 5 mA.
But somewhere around 7 mA, the upper curve in Figure 24
drops below 2.5 V (VREF) indicating that at these higher currents,
the output will not be capable of reaching VREF.
SOURCE/SINK CURRENT – mA
5
05
10
15
OUTPUT
VOLTAGE
V
4
3
2
1
0
DAC LOADED WITH 0000 HEX
DAC LOADED WITH 0FFF HEX
Figure 23. Source and Sink Current Capability
with VREF = AVDD = 5 V
SOURCE/SINK CURRENT – mA
4
05
10
15
OUTPUT
VOLTAGE
V
3
1
0
DAC LOADED WITH 0000 HEX
DAC LOADED WITH 0FFF HEX
Figure 24. Source and Sink Current Capability
with VREF = VDD = 3 V
For larger loads, the current drive capability may not be
sufficient. In order to increase the source and sink current
capability of the DAC, an external buffer should be added, as
shown in Figure 25.
ADuC834
12
Figure 25. Buffering the DAC Output
The DAC output buffer also features a high impedance disable
function. In the chip’s default power-on state, the DAC is
disabled and its output is in a high impedance state (or “three-
state”) where they remain inactive until enabled in software.
This means that if a zero output is desired during power-up or
power-down transient conditions, a pull-down resistor must be
added to each DAC output. Assuming this resistor is in place,
the DAC output will remain at ground potential whenever the
DAC is disabled.
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