參數(shù)資料
型號(hào)： ADUC834BCPZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 63/80頁(yè)
文件大?。?/td> 0K
描述： IC MCU 62K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 62KB（62K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x16b，4x24b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤(pán)，CSP
包裝： 帶卷 (TR)
REV. A
–66–
ADuC834
b.
DGND
AGND
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
c.
GND
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
a.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
DGND
AGND
Figure 64. System Grounding Schemes
If the user plans to connect fast logic signals (rise/fall time < 5 ns)
to any of the ADuC834’s digital inputs, add a series resistor to
each relevant line to keep rise and fall times longer than 5 ns at
the ADuC834 input pins. A value of 100
or 200 is usually
sufficient to prevent high speed signals from coupling capaci-
tively into the ADuC834 and affecting the accuracy of ADC
conversions.
ADuC834 System Self-Identification
In some hardware designs, it may be an advantage for the
software running on the ADuC834 target to identify the host
MicroConverter. For example, code running on the ADuC834
may also be used with the ADuC824 or the ADuC816, and is
required to operate differently.
The CHIPID SFR is a read-only register located at SFR
address C2H. The upper nibble of this SFR designates the
MicroConverter within the
Σ- ADC family. User software can
read this SFR to identify the host MicroConverter and thus
execute slightly different code if required. The CHIPID SFR reads
as follows for the
Σ- ADC family of MicroConverter products.
ADuC836
CHIPID = 3xH
ADuC834
CHIPID = 2xH
ADuC824
CHIPID = 0xH
ADuC816
CHIPID = 1xH
Clock Oscillator
As described earlier, the core clock frequency for the ADuC834
is generated from an on-chip PLL that locks onto a multiple
(384 times) of 32.768 kHz. The latter is generated from an
internal clock oscillator. To use the internal clock oscillator,
connect a 32.768 kHz parallel resonant crystal between XTAL1
and XTAL2 pins (32 and 33) as shown in Figure 65.
As shown in the typical external crystal connection diagram in
Figure 65, two internal 12 pF capacitors are provided on-chip.
These are connected internally, directly to the XTAL1 and
XTAL2 pins, and the total input capacitances at both pins is
detailed in the Specification section of this data sheet. The value
of the total load capacitance required for the external crystal
should be the value recommended by the crystal manufacturer
for use with that specific crystal. In many cases, because of the
on-chip capacitors, additional external load capacitors will not
be required.
XTAL2
XTAL1
32.768kHz
TO INTERNAL
PLL
ADuC834
12pF
32
33
Figure 65. External Parallel Resonant Crystal
Connections Other Hardware Considerations
To facilitate in-circuit programming, plus in-circuit debug and
emulation options, users will want to implement some simple
connection points in their hardware that will allow easy access
to Download, Debug, and Emulation modes.
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