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參數(shù)資料
| 型號(hào)： | ADUC834BCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 30/80頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 62KB（62K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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REV. A
–36–
ADuC834
Table XVI. PWMCON SFR Bit Designations
Bit
Name
Description
7
–––
Reserved for Future Use
6
MD2
PWM Mode Bits
5
MD1
The MD2/1/0 bits choose the PWM mode as follows:
4
MD0
MD2
MD1
MD0
Mode
0
00Mode 0: PWM Disabled
0
01Mode 1: Single Variable Resolution PWM
0
10Mode 2: Twin 8-bit PWM
0
11Mode 3: Twin 16-bit PWM
1
00Mode 4: Dual NRZ 16-bit -
DAC
1
01Mode 5: Dual 8-bit PWM
1
10Mode 6: Dual RZ 16-bit -
DAC
1
11Reserved for Future Use
3CDIV1
PWM Clock Divider
2CDIV0
Scale the clock source for the PWM counter as follows:
CDIV1
CDIV0 Description
00
PWM Counter = Selected Clock /1
01
PWM Counter = Selected Clock /4
10
PWM Counter = Selected Clock /16
11
PWM Counter = Selected Clock /64
1
CSEL1
PWM Clock Divider
0
CSEL0
Select the clock source for the PWM as follows:
CSEL1
CSEL0 Description
00
PWM Clock = fXTAL/15
01
PWM Clock = fXTAL
10
PWM Clock = External Input at P3.4/T0/PWMCLK
11
PWM Clock = fVCO (12.58 MHz)
PULSEWIDTH MODULATOR (PWM)
The PWM on the ADuC834 is a highly flexible PWM offering
programmable resolution and input clock, and can be config-
ured for any one of six different modes of operation. Two of
these modes allow the PWM to be configured as a -
DAC
with up to 16 bits of resolution. A block diagram of the PWM is
shown in Figure 26.
CLOCK
SELECT
PROGRAMMABLE
DIVIDER
COMPARE
MODE
PWM0H/L
PWM1H/L
12.583MHz
PWMCLK
32.768kHz
32.768kHz/15
P1.0
P1.1
16-BIT PWM COUNTER
Figure 26. PWM Block Diagram
The PWM uses five SFRs: the control SFR, PWMCON, and four
data SFRs PWM0H, PWM0L, PWM1H, and PWM1L.
PWMCON (as described below) controls the different modes of
operation of the PWM as well as the PWM clock frequency.
PWM0H/L and PWM1H/L are the data registers that determine
the duty cycles of the PWM outputs at P1.0 and P1.1.
To use the PWM user software, first write to PWMCON to
select the PWM mode of operation and the PWM input clock.
Writing to PWMCON also resets the PWM counter. In any of
the 16-bit modes of operation (Modes 1, 3, 4, 6), user software
should write to the PWM0L or PWM1L SFRs first. This value
is written to a hidden SFR. Writing to the PWM0H or PWM1H
SFRs updates both the PWMxH and the PWMxL SFRs but
does not change the outputs until the end of the PWM cycle in
progress. The values written to these 16-bit registers are then
used in the next PWM cycle.
PWMCON
PWM Control SFR
SFR Address
AEH
Power-On Default Value
00H
Bit Addressable
No
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