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| 型號： | ADUC832BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 76/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標準包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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ADuC832
Data Sheet
Rev. B | Page 78 of 92
CORE
CLK*
2
T2
PIN
TR2
CONTROL
TL2
(8 BITS)
TH2
(8 BITS)
RELOAD
EXEN2
CONTROL
T2EX
PIN
TRANSITION
DETECTOR
EXF 2
TIMER 2
INTERRUPT
NOTE AVAILABILITY OF ADDITIONAL
EXTERNAL INTERRUPT
*
CORE CLK IS DEFINED BY THE CD BITS IN PLLCON.
RCAP2L
RCAP2H
TIMER 2
OVERFLOW
2
16
RCLK
TCLK
RX
CLOCK
TX
CLOCK
0
1
0
SMOD
TIMER 1
OVERFLOW
C/T2 = 0
C/T2 = 1
OSC. FREQ. IS DIVIDED BY 2, NOT 12.
02987-
071
Figure 83. Timer 2, UART Baud Rates
TIMER 3 GENERATED BAUD RATES
The high integer dividers in a UART block mean that high
speed baud rates are not always possible using some particular
crystals. For example, using a 12 MHz crystal, a baud rate of
115,200 is not possible. To address this problem, the ADuC832
has a dedicated baud rate timer (Timer 3) specifically for
generating highly accurate baud rates.
Timer 3 can be used instead of Timer 1 or Timer 2 for generating
very accurate high speed UART baud rates including 115,200
and 230,400. Timer 3 also allows a much wider range of baud
rates to be obtained. Every desired bit rate from 12 bits/sec to
393,216 bits/sec can be generated to within an error of ±0.8%.
Timer 3 also frees up the other three timers, allowing them to
be used for different applications. A block diagram of Timer 3 is
shown in Figure 84.
÷ (1 + T3FD/64)
÷2
T3 RX/TX
CLOCK
CORE
CLK*
T3EN
RX
CLOCK
TX CLOCK
TIMER 1/TIMER 2
RX CLOCK (FIG 83)
FRACTIONAL
DIVIDER
0
1
TIMER 1/TIMER 2
TX CLOCK (FIG 83)
÷16
÷2DIV
*CORE CLK IS DEFINED BY THE CD BITS IN PLLCON.
02987-
072
Figure 84. Timer 3, UART Baud Rates
Two SFRs (T3CON and T3FD) are used to control Timer 3.
T3CON is the baud rate control SFR, allowing Timer 3 to be
used to set up the UART baud rate, and setting up the binary
divider (DIV).
Table 43. T3CON SFR Bit Designations
Bit
Name
Description
[7]
T3BAUDEN
T3 UART baud rate enable. Set to enable
Timer 3 to generate the baud rate. When
set, PCON[7], T2CON[4], and T2CON[5] are
ignored. Cleared to let the baud rate be
generated as per a standard 8052.
[6:4]
Reserved
[2:0]
DIV[2:0]
Binary divider factor
DIV2
DIV1
DIV0
Binary Divider
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
The appropriate value to write to the DIV[2:0] bits can be
calculated using the following formula
)
2
log(
32
log
×
=
Rate
Baud
f
DIV
CORE
where fCORE is defined in the PLLCON SFR, PLLCON[2:0].
Note that the DIV value must be rounded down.
T3FD is the fractional divider ratio required to achieve the
required baud rate. The appropriate value for T3FD can be
calculated using the following formula:
Rate
Baud
f
FD
T
DIV
CORE
×
=
2
3
Note that T3FD should be rounded to the nearest integer.
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