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參數(shù)資料
| 型號： | ADUC832BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 71/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標準包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC832
Rev. B | Page 73 of 92
TIMER/COUNTER 2
T2CON (TIMER/COUNTER 2 CONTROL REGISTER)
SFR Address:
C8H
Power-On Default Value:
00H
Bit Addressable:
Yes
TIMER/COUNTER 2 DATA REGISTERS
Timer/Counter 2 also has two pairs of 8-bit data registers
associated with it. These are used as both timer data registers
and timer capture/reload registers.
TH2 and TL2
TH2 is the Timer 2 data high byte and TL2 is the low byte. The
SFR addresses for TH2 and TL2 are CDH and CCH, respectively.
RCAP2H and RCAP2L
RCAP2H is the Timer 2 capture/reload high byte and RCAP2L
is the low byte. The SFR addresses for RCAP2H and RCAP2L
are CBH and CAH, respectively.
Table 38. T2CON SFR Bit Designations
Bit
Name
Description
[7]
TF2
Timer 2 overflow flag.
Set by hardware on a Timer 2 overflow. TF2 is not set when either RCLK = 1 or TCLK = 1.
Cleared by user software.
[6]
EXF2
Timer 2 external flag.
Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
Cleared by user software.
[5]
RCLK
Receive clock enable bit.
Set by the user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port Mode 1 and Mode 3.
Cleared by the user to enable Timer 1 overflow to be used for the receive clock.
[4]
TCLK
Transmit clock enable bit.
Set by the user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Mode 1 and
Mode 3. Cleared by the user to enable Timer 1 overflow to be used for the transmit clock.
[3]
EXEN2
Timer 2 external enable flag.
Set by the user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used
to clock the serial port.
Cleared by the user for Timer 2 to ignore events at T2EX.
[2]
TR2
Timer 2 start/stop control bit.
Set by the user to start Timer 2.
Cleared by the user to stop Timer 2.
[1]
CNT2
Timer 2 timer or counter function select bit.
Set by the user to select counter function (input from external T2 pin).
Cleared by the user to select timer function (input from on-chip core clock).
[0]
CAP2
Timer 2 capture/reload select bit.
Set by the user to enable captures on negative transitions at T2EX if EXEN2 = 1.
Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When
either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow.
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