- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1900 > ADUC832BSZ-REEL (Analog Devices Inc)IC MCU 62K FLASH ADC/DAC 52MQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADUC832BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 55/92頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 62KB（62K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)當(dāng)前第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)
Data Sheet
ADuC832
Rev. B | Page 59 of 92
SPIDAT (SPI Data Register)
SFR Address:
F7H
Power-On Default Value:
00H
Bit Addressable:
No
The SPIDAT SFR is written by the user to transmit data over the
SPI interface, or read by the user read data just received by the
SPI interface.
USING THE SPI INTERFACE
Depending on the configuration of the bits in the SPICON SFR
shown in Table 28, the ADuC832 SPI interface transmits or
receives data in a number of possible modes. Figure 63 shows all
possible ADuC832 SPI configurations and the timing relationships
and synchronization between the signals involved. Also shown
is the SPI interrupt bit (ISPI) and how it is triggered at the end of
each byte-wide communication.
SCLOCK
(CPOL = 1)
SCLOCK
(CPOL = 0)
(CPHA = 1)
(CPHA = 0)
SAMPLE INPUT
ISPI FLAG
DATA OUTPUT
ISPI FLAG
SAMPLE INPUT
DATA OUTPUT
×
MSB BIT 6 BIT 5
×
BIT4 BIT 3 BIT2 BIT1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
SS
02
987-
0
52
Figure 63. SPI Timing, All Modes
SPI INTERFACE—MASTER MODE
In master mode, the SCLOCK pin is always an output and
generates a burst of eight clocks whenever user code writes to
the SPIDAT register. The SCLOCK bit rate is determined by
SPR0 and SPR1 in SPICON. It should also be noted that the SS
pin is not used in master mode. If the ADuC832 needs to assert
the SS pin on an external slave device, a port digital output pin
should be used.
In master mode, a byte transmission or reception is initiated by
a write to SPIDAT. Eight clock periods are generated via the
SCLOCK pin and the SPIDAT byte being transmitted via MOSI.
With each SCLOCK period, a data bit is also sampled via MISO.
After eight clocks, the transmitted byte is completely transmitted
and the input byte waits in the input shift register. The ISPI flag
is set automatically and an interrupt occurs if enabled. The
value in the shift register is latched into SPIDAT.
SPI INTERFACE—SLAVE MODE
In slave mode, the SCLOCK is an input. The SS pin must also
be driven low externally during the byte communication.
Transmission is also initiated by a write to SPIDAT. In slave mode,
a data bit is transmitted via MISO and a data bit is received via
MOSI through each input SCLOCK period. After eight clocks,
the transmitted byte is completely transmitted and the input
byte waits in the input shift register. The ISPI flag is set automati-
cally and an interrupt occurs if enabled. The value in the shift
register is latched into SPIDAT only when the transmission/
reception of a byte has been completed. The end of transmission
occurs after the eighth clock has been received if CPHA = 1, or
when SS returns high if CPHA = 0.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADUC834BCPZ-REEL | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| ADUC836BCPZ | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| ADUC843BSZ62-5 | IC ADC 12BIT W/FLASH MCU 52-MQFP |
| ADUC845BCPZ62-5 | IC FLASH MCU W/24BIT ADC 56-CSP |
| ADUC847BCPZ62-5 | IC MCU FLASH W/24BIT ADC 56-CSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADUC832QS-U1 | 制造商:Analog Devices 功能描述:EVAL KIT - Bulk |
| ADUC834 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit/24-Bit ADCs with Embedded 62 kB Flash MCU |
| ADUC834_02 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit/24-Bit ADCs with Embedded 62 kB Flash MCU |
| ADUC834BCP | 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 62KB FLASH 12.58MHZ 3.3/5V 56LFCSP - Bulk 制造商:Analog Devices 功能描述: |
| ADUC834BCPZ | 功能描述:IC MCU 62K FLASH ADC/DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標(biāo)準(zhǔn)包裝:250 系列:LPC11Uxx 核心處理器:ARM? Cortex?-M0 芯體尺寸:32-位 速度:50MHz 連通性:I²C，Microwire，SPI，SSI，SSP，UART/USART，USB 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，POR，WDT 輸入/輸出數(shù):40 程序存儲(chǔ)器容量:96KB（96K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-LQFP 包裝:托盤(pán) 其它名稱:568-9587 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。