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| 型號： | ADUC832BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 65/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標準包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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ADuC832
Data Sheet
Rev. B | Page 68 of 92
them drive a logic low output voltage (VOL) and are capable of
sinking 1.6 mA.
P2.6 and P2.7 can also be used as PWM outputs. If they are
selected as the PWM outputs via the CFG832 SFR, the PWM
outputs overwrite anything written to P2.6 or P2.7.
CONTROL
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
Q
LATCH
ADDR
P2.x
PIN
INTERNAL
PULL-UP*
*SEE FIGURE 69 FOR
DETAILS OF INTERNAL PULL-UP
DVDD
02987-
057
Q
Figure 68. Port 2 Bit Latch and I/O Buffer
Q
FROM
PORT
LATCH
2 CLK
DELAY
Q1
DVDD
Q2
Q3
P2.x
PIN
Q4
DVDD
02987-
058
Figure 69. Internal Pull-Up Configuration
PORT 3
Port 3 is a bidirectional port with internal pull-ups directly
controlled via the P3 SFR. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and, in that state,
can be used as inputs. As inputs, Port 3 pins pulled externally
low source current because of the internal pull-ups. Port 3 pins
with 0s written to them drive a logic low output voltage (VOL)
and are capable of sinking 4 mA.
Port 3 pins also have various secondary functions described in
Table 35. The alternate functions of Port 3 pins can only be
activated if the corresponding bit latch in the P3 SFR contains a 1.
Otherwise, the port pin is stuck at 0.
Table 35. Port 3, Alternate Pin Functions
Pin
Alternate Function
P3.0
RxD (UART input pin or serial data I/O in Mode 0)
P3.1
TxD (UART output pin or serial clock output in Mode 0)
P3.2
INT0 (External Interrupt 0)
P3.3
INT1 (External Interrupt 1) or PWM1/MISO
P3.4
T0 (Timer/Counter 0 external input), PWMC, PWM0, or
EXTCLK
P3.5
T1 (Timer/Counter 1 external input) or CONVST
P3.6
WR (external data memory write strobe)
P3.7
RD (external data memory read strobe)
P3.3 and P3.4 can also be used as PWM outputs. If they are
selected as the PWM outputs via the CFG832 SFR, the PWM
outputs overwrite anything written to P3.4 or P3.3.
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
Q
LATCH
DVDD
P3.x
PIN
INTERNAL
PULL-UP*
*SEE FIGURE 69
FOR DETAILS OF
INTERNAL PULL-UP
ALTERNATE
OUTPUT
FUNCTION
ALTERNATE
INPUT
FUNCTION
02987-
059
Figure 70. Port 3 Bit Latch and I/O Buffer
ADDITIONAL DIGITAL I/O
In addition to the port pins, the dedicated SPI/I2C pins
(SCLOCK and SDATA/MOSI) also feature both input and
output functions. Their equivalent I/O architectures are
illustrated in Figure 71 and Figure 73, respectively, for SPI
Notice that in I2C mode (SPE, SPICON[5] = 0), the strong pull-
up FET (Q1) is disabled, leaving only a weak pull-up (Q2)
present. By contrast, in SPI mode (SPE = 1) the strong pull-up
FET (Q1) is controlled directly by SPI hardware, giving the pin
push-pull capability.
In I2C mode (SPE = 0), two pull-down FETs (Q3 and Q4)
operate in parallel to provide an extra 60% or 70% of current
sinking capability. In SPI mode, however, (SPE = 1) only one of
the pull-down FETs (Q3) operates on each pin, resulting in sink
capabilities identical to that of Port 0 and Port 2 pins. On the
input path of SCLOCK, notice that a Schmitt trigger conditions
the signal going to the SPI hardware to prevent false triggers
(double triggers) on slow incoming edges. For incoming signals
from the SCLOCK and SDATA pins going to I2C hardware, a filter
conditions the signals in order to reject glitches of up to 50 ns in
duration.
Notice also that direct access to the SCLOCK and SDATA/MOSI
pins is afforded through the SFR interface in I2C master mode.
Therefore, if the SPI or I2C functions are not used, these two
pins can be used to give additional high current digital outputs.
DVDD
HARDWARE SPI
(MASTER/SLAVE)
Q3
SCHMITT
TRIGGER
Q1
Q2 (OFF)
SCLOCK
PIN
Q4 (OFF)
SPE = 1 (SPI ENABLE)
02987-
060
Figure 71. SCLOCK Pin I/O Functional Equivalent in SPI Mode
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