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參數(shù)資料
| 型號： | ADUC832BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標準包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC832
Rev. B | Page 37 of 92
ADCCON2 (ADC Control SFR 2)
SFR Address:
D8H
SFR Power-On Default Value:
00H
Bit Addressable:
Yes
The ADCCON2 register controls ADC channel selection and
conversion modes as detailed in Table 17.
Table 17. ADCCON2 SFR Bit Designations
Bit
Name
Description
[7]
ADCI
The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at the end of a DMA block
conversion. ADCI is cleared by hardware when the PC vectors to the ADC interrupt service routine. Otherwise, the ADCI bit
should be cleared by user code.
[6]
DMA
The DMA mode enable bit (DMA) is set by the user to enable a preconfigured ADC DMA mode of operation. A more
detailed description of this mode is given in the ADC DMA Mode section. The DMA bit is automatically cleared to 0 at the
end of a DMA cycle. Setting this bit causes the ALE output to cease, starting again when DMA is started, and operates
correctly after DMA is complete.
[5]
CCONV
The continuous conversion bit (CCONV) is set by the user to initiate the ADC into a continuous mode of conversion. In this
mode, the ADC starts converting based on the timing and channel configuration already set up in the ADCCONx SFRs; the
ADC automatically starts another conversion once a previous conversion has completed.
[4]
SCONV
The single conversion bit (SCONV) is set to initiate a single conversion cycle. The SCONV bit is automatically reset to 0 on
completion of the single conversion cycle.
[3:0]
CS[3:0]
The channel selection bits (CS[3:0] allow the user to program the ADC channel selection under software control. When a
conversion is initiated, the channel converted is the one selected by these channel selection bits. In DMA mode, the
channel selection is derived from the channel ID written to the external memory.
CS3
CS2
CS1
CS0
Channel Number
0
1
0
1
0
2
0
1
3
0
1
0
4
0
1
0
1
5
0
1
0
6
0
1
7
1
0
Temperature sensor (requires minimum of 1 μs to acquire)
1
0
1
DAC0 (only use with internal DAC output buffer on)
1
0
1
0
DAC1 (only use with internal DAC output buffer on)
1
0
1
AGND
1
0
VREF
1
DMA stop (place in XRAM location to finish DMA sequence, see the ADC DMA
Mode section)
All other combinations reserved
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