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| 型號： | ADUC832BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 72/92頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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ADuC832
Data Sheet
Rev. B | Page 74 of 92
TIMER/COUNTER OPERATION MODES
The following sections describe the operating modes for Timer/
Counter 2. The operating modes are selected by bits in the T2CON
SFR as shown in Table 39.
Table 39. T2CON Operating Modes
RCLK (or) TCLK
CAP2
TR2
Mode
0
1
16-bit autoreload
0
1
16-bit capture
1
X
1
Baud rate
X
0
Off
16-Bit Autoreload Mode
In autoreload mode, there are two options, which are selected
by Bit EXEN2 in T2CON. If EXEN2 = 0, then when Timer 2
rolls over, it not only sets TF2 but also causes the Timer 2 regis-
ters to be reloaded with the 16-bit value in Register RCAP2L and
Register RCAP2H, which are preset by software. If EXEN2 = 1,
then Timer 2 still performs the same function as EXEN2 = 0,
but with the added feature that a 1-to-0 transition at External
Input T2EX also triggers the 16-bit reload and sets EXF2. The
autoreload mode is illustrated in Figure 79.
16-Bit Capture Mode
In the capture mode, there are again two options, which are
selected by Bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2
is a 16-bit timer or counter that, upon overflowing, sets Bit TF2,
the Timer 2 overflow bit, which can be used to generate an inter-
rupt. If EXEN2 = 1, then Timer 2 still performs the same function
as EXEN2 = 0, but a l-to-0 transition on External Input T2EX
causes the current value in the Timer 2 registers, TL2 and TH2,
to be captured into Register RCAP2L and Register RCAP2H,
respectively. In addition, the transition at T2EX causes Bit EXF2
in T2CON to be set, and EXF2, like TF2, can generate an inter-
rupt. The capture mode is illustrated in Figure 80.
The baud rate generator mode is selected by RCLK = 1 and/or
TCLK = 1.
In either case, if Timer 2 is being used to generate the baud rate,
the TF2 interrupt flag does not occur. Therefore, Timer 2 interrupts
do not occur, so they do not have to be disabled. In this mode,
the EXF2 flag, however, can still cause interrupts, and this can
be used as a third external interrupt.
Baud rate generation is described as part of the UART serial
port operation in the UART Serial Interface section.
CORE
CLK*
÷12
T2
PIN
C/T2 = 0
C/T2 = 1
TR2
CONTROL
TL2
(8 BITS)
TH2
(8 BITS)
RELOAD
TF2
EXF2
TIMER
INTERRUPT
EXEN2
CONTROL
TRANSITION
DETECTOR
T2EX
PIN
RCAP2L
*CORE CLK IS DEFINED BY THE CD BITS IN PLLCON.
RCAP2H
02987-
068
Figure 79. Timer/Counter 2, 16-Bit Autoreload Mode
TF2
CORE
CLK*
T2
PIN
TR2
CONTROL
TL2
(8 BITS)
TH2
(8 BITS)
CAPTURE
EXF2
TIMER
INTERRUPT
EXEN2
CONTROL
TRANSITION
DETECTOR
T2EX
PIN
RCAP2L
RCAP2H
C/T2 = 0
C/T2 = 1
*CORE CLK IS DEFINED BY THE CD BITS IN PLLCON.
÷12
02987-
069
Figure 80. Timer/Counter 2, 16-Bit Capture Mode
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