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參數資料
| 型號： | ADUC832BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 33/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標準包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數據轉換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC832
Rev. B | Page 39 of 92
DRIVING THE ANALOG-TO-DIGITAL CONVERTER
The ADC incorporates a successive approximation (SAR) architec-
ture involving a charge-sampled input stage. Figure 39 shows
the equivalent circuit of the analog input section. Each ADC
conversion is divided into two distinct phases as defined by the
position of the switches in Figure 39. During the sampling
phase (with SW1 and SW2 in the track position), a charge
proportional to the voltage on the analog input is developed
across the input sampling capacitor. During the conversion
phase (with both switches in the hold position) the capacitor
DAC is adjusted via internal SAR logic until the voltage on
Node A is 0, indicating that the sampled charge on the input
capacitor is balanced out by the charge being output by the
capacitor DAC. The digital value finally contained in the SAR
is then latched out as the result of the ADC conversion. Control
of the SAR, and timing of acquisition and sampling modes, is
handled automatically by built-in ADC control logic. Acquisi-
tion and conversion times are also fully configurable under user
control.
CAPACITOR
DAC
COMPARATOR
VREF
AGND
DAC1
DAC0
TEMPERATURE SENSOR
ADC7
ADC0
32pF
AGND
ADuC832
NODE A
SW1
SW2
TRACK
HOLD
200
02987-
028
Figure 39. Internal ADC Structure
Note that whenever a new input channel is selected, a residual
charge from the 32 pF sampling capacitor places a transient on
the newly selected input. The signal source must be capable of
recovering from this transient before the sampling switches are
changed to hold mode. Delays can be inserted in software
(between channel selection and conversion request) to account
for input stage settling, but a hardware solution alleviates this
burden from the software design task and ultimately results in a
cleaner system implementation. One hardware solution would
be to choose a very fast settling op amp to drive each analog
input. Such an op amp would need to fully settle from a small
signal transient in less than 300 ns to guarantee adequate
settling under all software configurations. A better solution,
recommended for use with any amplifier, is shown in Figure 40.
Though the circuit in Figure 40 may look like a simple
antialiasing filter, it actually serves no such purpose because its
corner frequency is well above the Nyquist frequency, even at a
200 kHz sample rate. Though the R/C does help to reject some
incoming high frequency noise, its primary function is to ensure
that the transient demands of the ADC input stage are met.
ADC0
ADuC832
10
0.1F
02987-
029
Figure 40. Buffering Analog Inputs
It does so by providing a capacitive bank from which the 32 pF
sampling capacitor can draw its charge. Its voltage does not
change by more than one count (1/4096) of the 12-bit transfer
function when the 32 pF charge from a previous channel is
dumped onto it. A larger capacitor can be used if desired, but
not a larger resistor, for the following reasons.
The Schottky diodes in Figure 40 may be necessary to limit
the voltage applied to the analog input pin as per the absolute
maximum ratings (see Table 12). They are not necessary if the
op amp is powered from the same supply as the ADuC832
because in that case the op amp is unable to generate voltages
above VDD or below ground. An op amp of some kind is neces-
sary unless the signal source is very low impedance to begin
with. DC leakage currents at the ADuC832 analog inputs can
cause measurable dc errors with external source impedances as
little as ~100 . To ensure accurate ADC operation, keep the
total source impedance at each analog input less than 61 .
Table 19 illustrates examples of how source impedance can
affect dc accuracy.
Table 19. Source Impedance Examples
Source
Impedance
Error from 1 μA
Leakage Current
Error from 10 μA
Leakage Current
61 Ω
61 μV = 0.1 LSB
610 μV = 1 LSB
610 Ω
610 μV = 1 LSB
6.1 mV = 10 LSB
Although Figure 40 shows the op amp operating at a gain of 1, it
can be configured for any gain needed. Also, an instrumentation
amplifier can be easily used in its place to condition differential
signals. Use any modern amplifier that is capable of delivering
the signal (0 V to VREF) with minimal saturation. Some single-
supply rail-to-rail op amps that are useful for this purpose
include, but are not limited to, the ones given in Table 20. Visit
www.analog.com for details on these and other op amps and
instrumentation amps.
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| ADUC834BCPZ | 功能描述:IC MCU 62K FLASH ADC/DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標準包裝:250 系列:LPC11Uxx 核心處理器:ARM? Cortex?-M0 芯體尺寸:32-位 速度:50MHz 連通性:I²C，Microwire，SPI，SSI，SSP，UART/USART，USB 外圍設備:欠壓檢測/復位，POR，WDT 輸入/輸出數:40 程序存儲器容量:96KB（96K x 8） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數據轉換器:A/D 8x10b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-LQFP 包裝:托盤 其它名稱:568-9587 |
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