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| 型號： | ADUC832BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 59/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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ADuC832
Data Sheet
Rev. B | Page 62 of 92
DUAL DATA POINTERS
The ADuC832 incorporates two data pointers. The second data
pointer is a shadow data pointer and is selected via the data
pointer control SFR (DPCON). DPCON also includes features
such as automatic hardware postincrement and postdecrement,
as well as automatic data pointer toggle. DPCON is described in
DPCON (DATA POINTER CONTROL SFR)
SFR Address:
A7H
Power-On Default Value:
00H
Bit Addressable:
No
Table 30. DPCON SFR Bit Designations
Bit
Name
Description
[7]
Reserved
Reserved for future use.
[6]
DPT
Data pointer automatic toggle enable.
Cleared by user to disable auto swapping of the DPTR. Set in user software to enable automatic toggling of the DPTR
after each MOVX or MOVC instruction.
[5:4]
DP1m[1:0]
Shadow data pointer mode.
These two bits enable extra modes of the shadow data pointer operation, allowing for more compact and more
efficient code size and execution.
DP1m1
DP1m0
Behavior of Shadow Data Pointer
0
8052 behavior
0
1
DPTR is postincremented after a MOVX or a MOVC instruction.
1
0
DPTR is postdecremented after a MOVX or MOVC instruction.
1
DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction can be useful for moving
8-bit blocks to/from 16-bit devices.)
[3:2]
DP0m[1:0]
Main data pointer mode. These two bits enable extra modes of the main data pointer operation, allowing for more
compact and more efficient code size and execution.
DP0m1
DP0m0
Behavior of the Main Data Pointer
0
8052 behavior
0
1
1 DPTR is postincremented after a MOVX or a MOVC instruction.
1
0
DPTR is postdecremented after a MOVX or MOVC instruction.
1
DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction can be useful for moving
8-bit blocks to/from 16-bit devices.)
[1]
Reserved
This bit is not implemented to allow the INC DPCON instruction to toggle the data pointer without incrementing the
rest of the SFR.
[0]
DPSEL
Data pointer select.
Cleared by user to select the main data pointer. This means that the contents of this 24-bit register are placed into the
DPL, DPH, and DPP SFRs.
Set by the user to select the shadow data pointer. This means that the contents of a separate 24-bit register appears in
the DPL, DPH, and DPP SFRs.
Notes
This is the only section where the main and shadow data
pointers are distinguished. Everywhere else in this data sheet
wherever the DPTR is mentioned, operation on the active
DPTR is implied.
Only MOVC/MOVX @DPTR instructions are relevant in Table 30.
MOVC/MOVX PC/@Ri instructions do not cause the DPTR to
automatically postincrement or postdecrement.
To illustrate the operation of DPCON, the following code copies
256 bytes of code memory at Address D000H into XRAM
starting from Address 0000H.
The following code uses 16 bytes and 2054 cycles. To perform
this on a standard 8051 requires approximately 33 bytes and
7172 cycles (depending on how it is implemented).
MOV
DPTR,#0
; Main DPTR = 0
MOV
DPCON,#55H
; Select shadow DPTR
; DPTR1 increment mode,
; DPTR0 increment mode
; DPTR auto toggling on
MOV
DPTR,#0D000H
; Shadow DPTR = D000H
MOVELOOP:
CLR
A
MOVC A,@A+DPTR
; Get data
; Post Inc DPTR
; Swap to Main DPTR (Data)
MOVX @DPTR,A
; Put ACC in XRAM
; Increment main DPTR
; Swap Shadow DPTR (Code)
MOV
A, DPL
JNZ
MOVELOOP
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