參數(shù)資料
型號： AD9957/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 9/64頁
文件大小： 0K
描述： BOARD EVAL AD9957 QUADRATURE MOD
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源： AD9957 Eval Brd Schematic
AD9957 BOM
AD9957 Gerber Files
標準包裝： 1
系列： AgileRF™
主要目的： 計時：DDS 調(diào)制器
嵌入式： 否
已用 IC / 零件： AD9957
主要屬性： 14 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬
次要屬性： 1GHz 圖形用戶界面
已供物品： 板，軟件
產(chǎn)品目錄頁面： 552 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD9957BSVZ-ND - IC DDS 1GSPS 14BIT IQ 100TQFP
AD9957BSVZ-REEL-ND - IC DDS 1GSPS 14BIT IQ 100TQFP
Data Sheet
AD9957
Rev. C | Page 17 of 64
QUADRATURE MODULATION MODE
A block diagram of the AD9957 operating in QDUC mode is
shown in Figure 26; grayed items are inactive. The parallel input
accepts 18-bit I- and Q-words in time-interleaved fashion. That
is, an 18-bit I-word is followed by an 18-bit Q-word, then the
next 18-bit I-word, and so on. One 18-bit I-word and one 18-bit
Q-word together comprise one internal sample. The data assem-
bler and formatter de-interleave the I- and Q-words so that each
sample propagates along the internal data pathway in parallel
fashion. Both I and Q data paths are active; the parallel data
clock (PDCLK) serves to synchronize the input of I/Q data to
the AD9957.
The PROFILE and I/O_UPDATE pins are also synchronous to
the PDCLK.
The DDS core provides a quadrature (sine and cosine) local
oscillator signal to the quadrature modulator, where the
interpolated I and Q samples are multiplied by the respective
phase of the carrier and summed together, producing a
quadrature modulated data stream. This data stream is routed
through the inverse sinc filter (optionally), and the output
scaling multiplier. Then it is applied to the 14-bit DAC to
produce the quadrature modulated analog output signal.
06384-
006
PDCLK
I/Q IN
E
X
T
_P
W
R_DW
N
DAC_RSET
IOUT
TxENABLE
DAC GAIN
OUTPUT
SCALE
FACTOR
θ
IN
VER
SE
S
INC
FILTE
R
CLOCK
FTW
PW
8
SYSCLK
PLL
÷2
CL
O
CK
M
O
DE
REF_CLK
REFCLK_OUT
XTAL_SEL
AD9957
ω
cos (ωt+θ)
sin (ωt+θ)
S
Y
NC_O
UT
S
Y
NC_I
N
P
LL_
LOC
K
P
LL_
LOOP
_
FI
L
T
ER
MA
ST
ER
_
R
ESET
2
O
SK
DDS
AUX
DAC
8-BIT
POWER
DOWN
CONTROL
18
D
AT
A
SSEMB
L
ER
AND
F
O
RM
A
TTE
R
I
Q
IS
QS
BL
ACKF
IN
I
NT
E
R
F
ACE
18
16
IN
VER
SE
CCI
IN
VER
SE
CCI
OSK
INTERNAL CLOCK TIMING AND CONTROL
DAC
14-BIT
CCI
_O
V
F
L
FTW
PW
PARALLEL DATA
TIMING AND CONTROL
RT
RAM
P
R
OFILE
SERIAL I/O
PORT
I/O_
U
P
D
A
TE
PROGRAMMING
REGISTERS
3
I Q
IS QS
HAL
F
-BAND
FI
L
T
ER
S
(4
×
)
CCI
(1×
T
O
63×
)
HAL
F
-BAND
FI
L
T
ER
S
(4
×
)
CCI
(1×
T
O
63×
)
S
DI
O
CS
I/
O
_
R
ESET
S
CL
K
S
DO
Figure 26. Quadrature Modulation Mode
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