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參數(shù)資料
| 型號(hào)： | AD9957/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 53/64頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AD9957 QUADRATURE MOD |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計(jì)資源： | AD9957 Eval Brd Schematic AD9957 BOM AD9957 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計(jì)時(shí)：DDS 調(diào)制器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9957 |
| 主要屬性： | 14 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬 |
| 次要屬性： | 1GHz 圖形用戶界面 |
| 已供物品： | 板，軟件 |
| 產(chǎn)品目錄頁(yè)面： | 552 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD9957BSVZ-ND - IC DDS 1GSPS 14BIT IQ 100TQFP AD9957BSVZ-REEL-ND - IC DDS 1GSPS 14BIT IQ 100TQFP |
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Data Sheet
AD9957
Rev. C | Page 57 of 64
Bit (s)
Mnemonic
Description
21:17
Open
16
Read Effective
FTW
0: a serial I/O port read operation of the FTW register reports the contents of the FTW register (default).
1: a serial I/O port read operation of the FTW register reports the actual 32-bit word appearing at the input to
the DDS phase accumulator.
15:14
I/O Update Rate
Control
Ineffective unless CFR2<23> = 1. Sets the prescale ratio of the divider that clocks the I/O update timer as
follows:
00: divide-by-1 (default).
01: divide-by-2.
10: divide-by-4.
11: divide-by-8.
13
PDCLK Rate
Control
Ineffective unless CFR2<31> = 0 and CFR1<25:24> = 00b.
0: PDCLK operates at the input data rate (default).
1: PDCLK operates at the input data rate; useful for maintaining a consistent relationship between I/Q
words at the parallel data port and the internal clocks of the baseband signal processing chain.
12
Data Format
0: the data-words applied to Pin D<17:0> are expected to be coded as twos complement (default).
1: the data-words applied to Pin D<17:0> are expected to be coded as offset binary.
11
PDCLK Enable
0: the PDCLK pin is disabled and forced to a static Logic 0 state; the internal clock signal continues to operate
and provide timing to the data assembler.
1: the internal PDCLK signal appears at the PDCLK pin (default).
10
PDCLK Invert
0: normal PDCLK polarity; Q-data associated with Logic 1, I-data with Logic 0 (default).
1: inverted PDCLK polarity.
9
TxEnable Invert
0: normal TxENABLE polarity; Logic 0 is standby, Logic 1 is transmit (default).
1: inverted TxENABLE polarity; Logic 0 is transmit, Logic 1 is standby.
8
Q-First Data
Pairing
0: an I/Q data pair is delivered as I-data first, followed by Q-data (default).
1: an I/Q data pair is delivered as Q-data first, followed by I-data.
7
Open
6
Data Assembler
Hold Last Value
Ineffective when CFR1<25:24> = 01b.
0: when the TxENABLE pin is false, the data assembler ignores the input data and internally forces zeros on
the baseband signal path (default).
1: when the TxENABLE pin is false, the data assembler ignores the input data and internally forces the last
value received on the baseband signal path.
5
Sync Timing
Validation Disable
0: enables the setup and hold validation circuit to take a measurement; the measurement result appears at
the SYNC_SMP_ERR pin; a Logic 1 at this pin indicates a potential setup/hold violation whereas a Logic 0
indicates that a setup/hold violation has not been detected; the measurement result is latched and held until
this bit is set to a Logic 1.
1: resets the setup and hold validation measurement circuit forcing the SYNC_SMP_ERR pin to a static Logic 0
condition (default); the measurement circuit is effectively disabled until this bit is restored to a Logic 0 state.
4:0
Open
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9958 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958 PCB | 制造商:Analog Devices 功能描述:EVAL BOARD ((NS)) |
| AD9958/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS |
| AD9958/PCBZ | 功能描述:BOARD EVALUATION FOR AD9958 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9958/PCBZ | 制造商:Analog Devices 功能描述:EVAL BOARD, AD9958 DIRECT DIGITAL SYNTHE |
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