參數(shù)資料
型號(hào)： AD9957/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/64頁(yè)
文件大小： 0K
描述： BOARD EVAL AD9957 QUADRATURE MOD
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： AD9957 Eval Brd Schematic
AD9957 BOM
AD9957 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： AgileRF™
主要目的： 計(jì)時(shí)：DDS 調(diào)制器
嵌入式： 否
已用 IC / 零件： AD9957
主要屬性： 14 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬
次要屬性： 1GHz 圖形用戶界面
已供物品： 板，軟件
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD9957BSVZ-ND - IC DDS 1GSPS 14BIT IQ 100TQFP
AD9957BSVZ-REEL-ND - IC DDS 1GSPS 14BIT IQ 100TQFP
AD9957
Data Sheet
Rev. C | Page 10 of 64
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
I/O1
Description
1, 24, 61, 72, 86,
87, 93, 97 to 100
NC
Not Connected. Allow device pin to float.
2
PLL_LOOP_FILTER
I
PLL-Loop Filter Compensation. See External PLL Loop Filter Components section.
3, 6, 89, 92
AVDD (1.8V)
I
Analog Core VDD. 1.8 V analog supplies.
74 to 77, 83
AVDD (3.3V)
I
Analog DAC VDD. 3.3 V analog supplies.
17, 23, 30, 47, 57,
64
DVDD (1.8V)
I
Digital Core VDD. 1.8 V digital supplies.
11, 15, 21, 28, 45,
56, 66
DVDD_I/O (3.3V)
I
Digital Input/Output VDD. 3.3 V digital supplies.
4, 5, 73, 78, 79,
82, 85, 88, 96
AGND
I
Analog Ground.
13, 16, 22, 29, 46,
58, 62, 63, 65
DGND
I
Digital Ground.
7
SYNC_IN+
I
Synchronization Signal, Digital Input (Rising Edge Active). Synchronization signal from
external master to synchronize internal subclocks. See the Synchronization of Multiple
Devices section.
8
SYNC_IN
I
Synchronization Signal, Digital Input (Falling Edge Active). Synchronization signal from
external master to synchronize internal subclocks. See the Synchronization of Multiple
Devices section.
9
SYNC_OUT+
O
Synchronization Signal, Digital Output (Rising Edge Active). Synchronization signal from
internal device subclocks to synchronize external slave devices. See the Synchronization of
10
SYNC_OUT
O
Synchronization Signal, Digital Output (Falling Edge Active). Synchronization signal from
internal device subclocks to synchronize external slave devices. See the Synchronization of
12
SYNC_SMP_ERR
O
Synchronization Sample Error, Digital Output (Active High). A high on this pin indicates
that the AD9957 did not receive a valid sync signal on SYNC_IN+/SYNC_IN. See the
14
MASTER_RESET
I
Master Reset, Digital Input (Active High). This pin clears all memory elements and sets
registers to default values.
18
EXT_PWR_DWN
I
External Power-Down, Digital Input (Active High). A high level on this pin initiates the
currently programmed power-down mode. See the Power-Down Control section for
further details. If unused, tie to ground.
19
PLL_LOCK
O
PLL Lock, Digital Output (Active High). A high on this pin indicates that the clock multiplier
PLL has acquired lock to the reference clock input.
20
CCI_OVFL
O
CCI Overflow Digital Output, Active High. A high on this pin indicates a CCI filter overflow.
This pin remains high until the CCI overflow condition is cleared.
25 to 27, 31 to
39, 42 to 44, 48
to 50
D<17:0>
I/O
Parallel Data Input Bus (Active High). These pins provide the interleaved, 18-bit, digital, I
and Q vectors for the modulator to upconvert. Also used for a GPIO port in Blackfin
interface mode.
42
SPORT I-DATA
I
In Blackfin interface mode, this pin serves as the I-data serial input.
43
SPORT Q-DATA
I
In Blackfin interface mode, this pin serves as the Q-data serial input.
40
PDCLK
O
Parallel Data Clock, Digital Output (Clock). See the Signal Processing section for details.
41
TxENABLE/FS
I
Transmit Enable, Digital Input (Active High). See the Signal Processing section for details.
In Blackfin interface mode, this pin serves as the FS input to receive the RFS output signal
from the Blackfin.
51
RT
I
RAM Trigger, Digital Input (Active High). This pin provides control for the RAM amplitude
scaling function. When this function is engaged, a high sweeps the amplitude from the
beginning RAM address to the end. A low sweeps the amplitude from the end RAM
address to the beginning. If unused, connect to ground or supply.
52 to 54
PROFILE<2:0>
I
Profile Select Pins, Digital Inputs (Active High). These pins select one of eight
phase/frequency profiles for the DDS core (single tone or carrier tone). Changing the state
of one of these pins transfers the current contents of all I/O buffers to the corresponding
registers. State changes should be set up to the SYNC_CLK pin.
55
SYNC_CLK
O
Output System Clock/4, Digital Output (Clock). The I/O_UPDATE and PROFILE<2:0> pins
should be set up to the rising edge of this signal.
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