參數(shù)資料
型號: AD9959/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 1/44頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9959
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源: Phase Coherent FSK Modulator (CN0186)
AD9958/59 Eval Brd Schematics
AD9958/59 Eval Brd Gerber Files
AD9959 Eval Brd BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,直接數(shù)字合成(DDS)
嵌入式:
已用 IC / 零件: AD9959
主要屬性: 10 位數(shù)模轉(zhuǎn)換器,32 位調(diào)節(jié)字寬
次要屬性: 4 通道
已供物品: 板,線纜,軟件
其它名稱: AD9959/PCB
AD9959/PCB-ND
Q2548077
4-Channel, 500 MSPS DDS
with 10-Bit DACs
AD9959
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005–2008 Analog Devices, Inc. All rights reserved.
FEATURES
4 synchronized DDS channels @ 500 MSPS
Independent frequency/phase/amplitude control between
channels
Matched latencies for frequency/phase/amplitude changes
Excellent channel-to-channel isolation (>65 dB)
Linear frequency/phase/amplitude sweeping capability
Up to 16 levels of frequency/phase/amplitude modulation
(pin-selectable)
4 integrated 10-bit digital-to-analog converters (DACs)
Individually programmable DAC full-scale currents
0.12 Hz or better frequency tuning resolution
14-bit phase offset resolution
10-bit output amplitude scaling resolution
Serial I/O port interface (SPI) with enhanced data throughput
Software-/hardware-controlled power-down
Dual supply operation (1.8 V DDS core/3.3 V serial I/O)
Multiple device synchronization
Selectable 4× to 20× REFCLK multiplier (PLL)
Selectable REFCLK crystal oscillator
56-lead LFCSP package
APPLICATIONS
Agile local oscillators
Phased array radars/sonars
Instrumentation
Synchronized clocking
RF source for AOTF
FUNCTIONAL BLOCK DIAGRAM
(4)
500MSPS
DDS CORES
REF CLOCK
INPUT CIRCUITRY
TIMING AND
CONTROL
MODULATION
CONTROL
SYSTEM
CLOCK
SOURCE
USER INTERFACE
RECONSTRUCTED
SINE WAVE
RECONSTRUCTED
SINE WAVE
RECONSTRUCTED
SINE WAVE
RECONSTRUCTED
SINE WAVE
10-BIT DAC
05
24
6-
1
01
Figure 1.
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