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參數(shù)資料
型號(hào): AD9957/PCBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 27/64頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL AD9957 QUADRATURE MOD
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源: AD9957 Eval Brd Schematic
AD9957 BOM
AD9957 Gerber Files
標(biāo)準(zhǔn)包裝: 1
系列: AgileRF™
主要目的: 計(jì)時(shí):DDS 調(diào)制器
嵌入式:
已用 IC / 零件: AD9957
主要屬性: 14 位數(shù)模轉(zhuǎn)換器,32 位調(diào)節(jié)字寬
次要屬性: 1GHz 圖形用戶界面
已供物品: 板,軟件
產(chǎn)品目錄頁(yè)面: 552 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: AD9957BSVZ-ND - IC DDS 1GSPS 14BIT IQ 100TQFP
AD9957BSVZ-REEL-ND - IC DDS 1GSPS 14BIT IQ 100TQFP
Data Sheet
AD9957
Rev. C | Page 33 of 64
06384-
026
START ADDRESS
END ADDRESS
1
2
3
4
5
RAM ADRESS
Δt
1 PDCLK CYCLE
OR
M DDS CLOCK CYCLES
I/O_UPDATE OR
RT TRANSITION
Figure 46. Continuous Recirculate Timing Diagram
RAM Continuous Recirculate Mode
The continuous recirculate mode mimics ramp-up mode,
except that when the state machine reaches the end address of
the active RAM segment register, it does not halt. Instead, the
next timeout of the internal timer causes the state machine to
jump to the start address of the active RAM segment register.
This process continues indefinitely until an I/O update or state
change on the RT pin. A state change on the RT pin aborts the
current waveform and the newly selected RAM segment register
initiates a new waveform.
A graphic representation of the continuous recirculate mode is
The circled numbers in Figure 46 indicate specific events, which
are explained as follows:
Event 1—an I/O update or state change on the RT pin occurs.
This initializes the state machine to the start address of the
active RAM segment register and causes the state machine to
begin incrementing the address counter at the appropriate rate.
Event 2—the state machine reaches the end address of the active
RAM segment register.
Event 3—the state machine switches to the start address of the
active RAM segment register. The state machine continues to
increment the address counter.
Event 4—the state machine again reaches the end address of the
active RAM segment register.
Event 5—the state machine switches to the start address of the
active RAM segment register. The state machine continues to
increment the address counter.
Event 4 and Event 5 repeat until an I/O update or state change
occurs on the RT pin.
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