參數(shù)資料
型號(hào)： AD9957/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 10/64頁
文件大?。?/td> 0K
描述： BOARD EVAL AD9957 QUADRATURE MOD
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： AD9957 Eval Brd Schematic
AD9957 BOM
AD9957 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： AgileRF™
主要目的： 計(jì)時(shí)：DDS 調(diào)制器
嵌入式： 否
已用 IC / 零件： AD9957
主要屬性： 14 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬
次要屬性： 1GHz 圖形用戶界面
已供物品： 板，軟件
產(chǎn)品目錄頁面： 552 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD9957BSVZ-ND - IC DDS 1GSPS 14BIT IQ 100TQFP
AD9957BSVZ-REEL-ND - IC DDS 1GSPS 14BIT IQ 100TQFP
AD9957
Data Sheet
Rev. C | Page 18 of 64
BLACKFIN INTERFACE (BFI) MODE
A subset of the QDUC mode is the Blackfin interface (BFI)
mode, shown in Figure 27; grayed items are inactive. In this
mode, a separate I and Q serial bit stream is applied to the
baseband data port instead of parallel data-words. The two
serial inputs provide for 16-bit I- and Q-words (unlike the
18-bit words in normal QDUC mode). The serial bit streams
are delivered to the Blackfin interface. The Blackfin interface
converts the 16-bit serial data into 16-bit parallel data to
propagate down the signal processing chain.
The Blackfin interface includes an additional pair of half-band
filters in both I and Q signal paths (not shown explicitly in the
diagram). The two half-band filters increase the interpolation
of the baseband data by a factor of four, relative to the normal
QDUC mode.
The synchronization of the serial data occurs through the
PDCLK signal. In BFI mode, the PDCLK signal is effectively
the bit clock for the serial data.
Note that the system clock is limited to 750 MHz in BFI mode.
06384-
007
PDCLK
I/Q IN
E
X
T
_P
W
R_DW
N
DAC_RSET
IOUT
TxENABLE
DAC GAIN
θ
IN
VER
SE
S
INC
FILTE
R
CLOCK
FTW
PW
8
SYSCLK
PLL
÷2
CL
O
CK
M
O
DE
REF_CLK
REFCLK_OUT
XTAL_SEL
AD9957
ω
cos (ωt+θ)
sin (ωt+θ)
S
Y
NC_O
UT
S
Y
NC_I
N
P
LL_
LOC
K
P
LL_
LOOP
_
FI
L
T
ER
MA
ST
ER
_
R
ESET
2
O
SK
DDS
AUX
DAC
8-BIT
POWER
DOWN
CONTROL
2
D
AT
A
SSEMB
L
ER
AND
F
O
RM
A
TTE
R
I
Q
IS
QS
BL
ACKF
IN
I
NT
E
R
F
ACE
18
16
IN
VER
SE
CCI
IN
VER
SE
CCI
OSK
INTERNAL CLOCK TIMING AND CONTROL
DAC
14-BIT
CCI
_O
V
F
L
O
SK
FTW
PW
PARALLEL DATA
TIMING AND CONTROL
RT
RAM
P
R
OFILE
SERIAL I/O
PORT
I/O_
U
P
D
A
TE
PROGRAMMING
REGISTERS
3
I Q
IS QS
HAL
F
-BAND
FI
L
T
ER
S
(4
×
)
CCI
(1×
T
O
63×
)
HAL
F
-BAND
FI
L
T
ER
S
(4
×
)
CCI
(1×
T
O
63×
)
OUTPUT
SCALE
FACTOR
S
DI
O
CS
I/
O
_
R
ESET
S
CL
K
S
DO
Figure 27. Quadrature Modulation Mode, Blackfin Interface
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