參數資料
型號： AD9957/PCBZ
廠商： Analog Devices Inc
文件頁數： 38/64頁
文件大?。?/td> 0K
描述： BOARD EVAL AD9957 QUADRATURE MOD
產品培訓模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設計資源： AD9957 Eval Brd Schematic
AD9957 BOM
AD9957 Gerber Files
標準包裝： 1
系列： AgileRF™
主要目的： 計時：DDS 調制器
嵌入式： 否
已用 IC / 零件： AD9957
主要屬性： 14 位數模轉換器，32 位調節(jié)字寬
次要屬性： 1GHz 圖形用戶界面
已供物品： 板，軟件
產品目錄頁面： 552 (CN2011-ZH PDF)
相關產品： AD9957BSVZ-ND - IC DDS 1GSPS 14BIT IQ 100TQFP
AD9957BSVZ-REEL-ND - IC DDS 1GSPS 14BIT IQ 100TQFP
Data Sheet
AD9957
Rev. C | Page 43 of 64
The validation result latch is in a reset state whenever the sync
receiver is disabled, which forces the SYNC_SMP_ERR pin to a
Logic 0 state. To reset the validation result latch when the sync
receiver is active, however, requires the use of the Sync Timing
Validation Disable bit in the multichip sync register. To make a
setup/hold validation measurement is a two-step process. First,
write a Logic 1 to the sync timing validation disable bit. Then,
to make a measurement, write a Logic 0. The first action resets
the validation result latch and holds it in a reset state; the
second action releases the reset state and enables the validation
result latch to capture a setup/hold validation measurement.
Each time a new setup/hold validation check is desired, this
two-step procedure must be performed.
Because the programmed value of the sync validation delay
establishes the time window for a setup/hold measurement,
the amount of delay is an important consideration for proper
operation of the validation block. The value chosen should
represent a small fraction of the SYSCLK period. For example,
if the SYSCLK frequency is 1 GHz (1000 ps period), then a
reasonable sync validation delay value is 4 (~300 ps). This
allows the validation block to ensure that the local SYSCLK
and the delayed SYNC_IN edges exhibit at least 300 ps of
timing separation. Choosing too large a value can cause the
validation block to indicate a setup/hold violation when one
does not exist. Choosing too small a value can cause the
validation block to miss a setup/hold violation when one
actually exists.
SYNC
PULSE
SYSCLK
DELAY
CHE
CK
L
O
G
IC
4
SYNC VALIDATION
DELAY
SYNC_SMP_ERR
SYNC RECEIVER
SYNC TIMING VALIDATION DISABLE
SETUP
VALIDATION
HOLD
VALIDATION
12
SETUP AND HOLD VALIDATION
TO
CLOCK
GENERATION
LOGIC
FROM
SYNC
RECEIVER
DELAY
LOGIC
D Q
DELAY
RISING EDGE
DETECTOR
AND STROBE
GENERATOR
06384-
036
4
Figure 58. Sync Timing Validation Block
相關PDF資料
PDF描述
GCA22DRMD-S288 CONN EDGECARD 44POS .125 EXTEND
AD9959/PCBZ BOARD EVALUATION FOR AD9959
ECM12DTKT-S288 CONN EDGECARD 24POS .156 EXTEND
ATWEBDVK-02RC KIT DEV TCP/IP AT89C51RD2 REMOTE
KSZ8862-10FL-EVAL BOARD EVALUATION KSZ8862-10FL
相關代理商/技術參數
參數描述
AD9958 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs
AD9958 PCB 制造商:Analog Devices 功能描述:EVAL BOARD ((NS))
AD9958/PCB 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS
AD9958/PCBZ 功能描述:BOARD EVALUATION FOR AD9958 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9958/PCBZ 制造商:Analog Devices 功能描述:EVAL BOARD, AD9958 DIRECT DIGITAL SYNTHE
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