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參數(shù)資料
| 型號(hào)： | AD9957/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD9957 QUADRATURE MOD |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計(jì)資源： | AD9957 Eval Brd Schematic AD9957 BOM AD9957 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計(jì)時(shí)：DDS 調(diào)制器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9957 |
| 主要屬性： | 14 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬 |
| 次要屬性： | 1GHz 圖形用戶界面 |
| 已供物品： | 板，軟件 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD9957BSVZ-ND - IC DDS 1GSPS 14BIT IQ 100TQFP AD9957BSVZ-REEL-ND - IC DDS 1GSPS 14BIT IQ 100TQFP |
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Data Sheet
AD9957
Rev. C | Page 45 of 64
I/Q PATH LATENCY
The I/Q latency through the AD9957 is easiest to describe in
terms of system clock (SYSCLK) cycles and is a function of the
AD9957 configuration (that is, which mode and which optional
features are engaged). The I/Q latency is primarily affected by
the programmable CCI rate.
The values in Table 12 should be considered estimates because
observed latency may be data dependent. The latency was
calculated using the linear delay model for FIR filters. N = CCI
rate (programmable interpolation rate, 2 to 63, 1 if bypassed).
In BFI mode, the latency through the AD9957 may not be con-
stant for multiple transmissions. This is due to the relationship
between the phase of the clock that drives the first half-band
filter and the frame sync signal coming from the Blackfin,
which is unknown and denoted as x in Table 12. The design
successfully transfers data from the data assembler logic to the
signal process path by updating a parallel register at the proper
time. The data is transferred from the parallel register to the
signal processing chain and all timing has been verified regard-
less of the phase relationship between the updating of the parallel
register and the signal processing clock.
Example
Quadrature modulation mode = 18-bit parallel data
Reference clock multiplier = bypassed
Input scale multiplier = off
Inverse CCI = off
CCI rate = 20
Inverse SINC = on
Output scale = off
Latency = (16 × 20) + (4 × 20) + (4 × 20) + (69 × 20) +
(4 × 20 + 8) + 22 + 8 + 2 + 8 = 1988 SYSCLKs
Table 12.
Stage
Quadrature Modulation Mode—Parallel
Quadrature Modulation Mode—BFI
Interpolation DAC Mode
Input Demuxplexer
16N
(16 + x)N
28N
where x = 0 to 15
Input Scale Multiplier
Active: 8N
Not available in BFI mode
Active: 8N
Bypassed: 4N
Inverse CCI Filter
Active: 8N
Bypassed: 4N
Half-Band Filters
69N
345N
69N
CCI Filter
Active: 4N + 8
Bypass: 2N + 4
Modulator
22
0
Inverse Sinc Filter
Active: 8
Bypass: 2
Output Scale Multiplier
Active: 12
Bypass: 2
DAC Interface
8
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