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參數(shù)資料
| 型號： | AD9549A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 57/76頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9549A |
| 設(shè)計資源： | AD9549 Schematics AD9549 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9549A |
| 主要屬性： | 8 kHz ~ 750 MHz 輸入 |
| 次要屬性： | 差分輸出 |
| 已供物品： | 板 |
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AD9549
Rev. D | Page 60 of 76
Register 0x0121—FTW Upper Limit
Table 53.
Bits
Bit Name
Description
[7:0]
FTW upper limit
Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x0122—FTW Upper Limit (Continued)
Table 54.
Bits
Bit Name
Description
[15:8]
FTW upper limit
Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x0123—FTW Upper Limit (Continued)
Table 55.
Bits
Bit Name
Description
[23:16]
FTW upper limit
Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x0124—FTW Upper Limit (Continued)
Table 56.
Bits
Bit Name
Description
[31:24]
FTW upper limit
Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x0125—FTW Upper Limit (Continued)
Table 57.
Bits
Bit Name
Description
[39:32]
FTW upper limit
Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x0126—FTW Upper Limit (Continued)
Table 58.
Bits
Bit Name
Description
[47:40]
FTW upper limit
Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x0127 to Register 0x012C—Frequency Slew Limit
Table 59.
Bits
Bit Name
Description
[47:0]
Frequency slew limit
See the Frequency Slew Limiter section.
Register 0x012D to Register 0x0130—Reserved
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