參數(shù)資料
型號: AD9146BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 9/56頁
文件大?。?/td> 0K
描述: IC DAC 16BIT SRL DUAL 48LFCSP
標(biāo)準(zhǔn)包裝: 1
系列: TxDAC+®
設(shè)置時(shí)間: 20ns
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-WQ(7x7)
包裝: 托盤
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 1.23G
Data Sheet
AD9146
Rev. A | Page 17 of 56
SERIAL PORT OPTIONS
The serial port can support both MSB first and LSB first data
formats. This functionality is controlled by the LSB_FIRST bit
(Register 0x00, Bit 6). The default is MSB first (LSB_FIRST = 0).
When LSB_FIRST = 0 (MSB first), the instruction and data bits
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent data
bytes should follow from high address to low address. In MSB first
mode, the serial port internal byte address generator decrements
for each data byte of the multibyte communication cycle.
When LSB_FIRST = 1 (LSB first), the instruction and data bits
must be written from LSB to MSB. Multibyte data transfers in
LSB first format start with an instruction byte that includes the
register address of the least significant data byte. Subsequent data
bytes should follow from low address to high address. In LSB first
mode, the serial port internal byte address generator increments
for each data byte of the multibyte communication cycle.
If the MSB first mode is active, the serial port controller data
address decrements from the data address written toward 0x00
for multibyte I/O operations. If the LSB first mode is active, the
serial port controller data address increments from the data
address written toward 0x7F for multibyte I/O operations.
R/W A6
A5
A4 A3
A2
A1
A0 D7N D6N D5N
D00
D10
D20
D30
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDIO
09691-
033
CS
Figure 26. Serial Port Interface Timing, MSB First
SCLK
SDIO
CS
A0
A1
A2
A3 A4
A5
A6 R/W D00 D10 D20
D7N
D6N
D5N
D4N
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
09691-
034
Figure 27. Serial Port Interface Timing, LSB First
SCLK
SDIO
CS
INSTRUCTION BIT 6
INSTRUCTION BIT 7
tDCSB
tDS
tDH
tPWH
tPWL
tSCLK
09691-
035
Figure 28. Timing Diagram for Serial Port Register Write
SCLK
SDIO
CS
DATA BIT n – 1
DATA BIT n
tDV
09691-
036
Figure 29. Timing Diagram for Serial Port Register Read
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