- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8959 > AD9146BCPZ (Analog Devices Inc)IC DAC 16BIT SRL DUAL 48LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9146BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 41/56頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SRL DUAL 48LFCSP |
| 標準包裝： | 1 |
| 系列： | TxDAC+® |
| 設置時間： | 20ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-WQ（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 1.23G |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
AD9146
Data Sheet
Rev. A | Page 46 of 56
REFCLKP(1)/
REFCLKN(1)
REFCLKP(2)/
REFCLKN(2)
DCIP(2)/
DCIN(2)
FRAMEP(2)/
FRAMEN(2)
tSKEW
tSDCI
tHDCI
09691-
070
Figure 63. Timing Diagram Required for Synchronizing Devices
DACCLKP/
DACCLKN
FRAMEP/
FRAMEN
REFCLKP/
REFCLKN
DCIP/
DCIN
IOUT1P/
IOUT1N
DCIP/
DCIN
DACCLKP/
DACCLKN
REFCLKP/
REFCLKN
FRAMEP/
FRAMEN
IOUT2P/
IOUT2N
SAMPLE
RATE CLOCK
LOW SKEW
CLOCK DRIVER
SYNC
CLOCK
LOW SKEW
CLOCK DRIVER
MATCHED
LENGTH TRACES
FPGA
09691-
071
Figure 64. Typical Circuit Diagram for Synchronizing Devices to a System Clock
To maintain synchronization, the skew between the REFCLK
signals of the devices must be less than tSKEW ns. When resetting
the FIFO, the FRAME signal must be held high for the time
interval required to write two complete input data words. A
timing diagram of the input signals is shown in Figure 63.
Figure 63 shows a REFCLK frequency equal to the data rate.
Although this is the most common situation, it is not strictly
required for proper synchronization. Any REFCLK frequency
that satisfies the following equation is acceptable. (This equation
is valid only when the PLL is used because only data rate mode
is available with the PLL on.)
fSYNC_I = fDACCLK/2N and fSYNC_I ≤ fDATA
where N = 0, 1, 2, or 3.
As an example, a configuration with 4× interpolation and clock
frequencies of fVCO = 1600 MHz, fDACCLK = 800 MHz, fDATA =
200 MHz, and fSYNC_I = 100 MHz is a viable solution.
SYNCHRONIZATION WITH DIRECT CLOCKING
When directly sourcing the DAC sample rate clock, a separate
REFCLK input signal is required for synchronization. To syn-
chronize devices, the DACCLK signal and the REFCLK signal
must be distributed with low skew to all the devices being syn-
chronized. If the devices need to be synchronized to a master
clock, use the master clock directly for generating the REFCLK
input (see Figure 64).
DATA RATE MODE SYNCHRONIZATION
Sourcing the DAC Sampling Clock section outlines the steps
required to synchronize multiple devices in data rate mode.
The procedure assumes that the DACCLK and REFCLK signals
are applied to all the devices. The following procedure must be
carried out on each individual device.
Procedure for Data Rate Synchronization When Directly
Sourcing the DAC Sampling Clock
Configure the AD9146 for data rate, periodic synchronization
by writing 0xC8 to the sync control register (Register 0x10).
Additional synchronization options are available (see the
Additional Synchronization Features section).
Read the sync locked bit (Register 0x12, Bit 6) to verify that the
device is back-end synchronized. A high level on this bit indicates
that the clocks are running with a constant and known phase
relative to the synchronization signal.
相關PDF資料 |
PDF描述 |
|---|---|
| GTC02R-36-5P | CONN RCPT 4POS BOX MNT W/PINS |
| VE-2TY-MX-F2 | CONVERTER MOD DC/DC 3.3V 49.5W |
| MS27508E24B4PC | CONN RCPT 56POS BOX MNT W/PINS |
| VE-2TY-MW-F2 | CONVERTER MOD DC/DC 3.3V 66W |
| MS27508E24B4PB | CONN RCPT 56POS BOX MNT W/PINS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9146BCPZRL | 功能描述:IC DAC 16BIT SRL DUAL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC+® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD9146-EBZ | 制造商:Analog Devices 功能描述:16 BIT DUAL SIGNAL PROC DAC EB - Boxed Product (Development Kits) |
| AD9146-M5375-EBZ | 功能描述:BOARD EVAL FOR AD9146 DAC RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9148 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter |
| AD9148ARUZ | 制造商:Analog Devices 功能描述:- Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。