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參數(shù)資料
型號： AD9146BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 35/56頁
文件大?。?/td> 0K
描述： IC DAC 16BIT SRL DUAL 48LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC+®
設(shè)置時間： 20ns
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-WQ（7x7）
包裝： 托盤
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 1.23G
AD9146
Data Sheet
Rev. A | Page 40 of 56
Figure 52 shows the most basic transmit DAC output circuitry.
A pair of resistors, RO, is used to convert each of the comple-
mentary output currents to a differential voltage output, VOUT.
Because the current outputs of the DAC are high impedance,
the differential driving point impedance of the DAC outputs,
ROUT, is equal to 2 × RO. Figure 53 illustrates the output voltage
waveforms.
RO
VIP +
VIN –
VOUTI
IOUT1P
IOUT1N
RO
VQP +
VQN –
VOUTQ
IOUT2P
IOUT2N
09691-
057
Figure 52. Basic Transmit DAC Output Circuit
+VPEAK
VP
VOUT
VN
VCM
0
–VPEAK
09691-
058
Figure 53. Output Voltage Waveforms
The common-mode signal voltage, VCM, is calculated as
O
FS
CM
R
I
V
×
=
2
The peak output voltage, VPEAK, is calculated as
VPEAK = IFS × RO
With this circuit configuration, the single-ended peak voltage is
the same as the peak differential output voltage.
Transmit DAC Linear Output Signal Swing
To achieve optimum performance, the DAC outputs have a
linear output compliance voltage range that must be adhered
to. The linear output signal swing is dependent on the full-scale
output current, IFS, and the common-mode level of the output.
Figure 54 shows the IMD performance vs. the output common-
mode voltage at different full-scale currents.
–85
–80
–75
–70
–65
–60
–55
–50
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
IM
D
(
d
Bc)
IFS = 10mA
IFS = 20mA
IFS = 30mA
VCM (V)
09691-
004
Figure 54. IMD vs. Output Common-Mode Voltage (fOUT = 161 MHz,
RLOAD = 50 Differential, IFS = 10 mA, 20 mA, and 30 mA)
AUXILIARY DAC OPERATION
The AD9146 has two auxiliary DACs: one associated with the
I path and one associated with the Q path. These auxiliary DACs
can be used to compensate for dc offsets in the transmitted signal.
Each auxiliary DAC has a single-ended current that can sink or
source current into either the positive (P) or negative (N) out-
put of the associated transmit DAC. The auxiliary DAC
structure is shown in Figure 55.
IOUT1P
IOUT1N
I DAC
VB
I AUX DAC
CURRENT
DIRECTION
I AUX DAC[9:0]
I AUX DAC
SIGN
09691-
061
Figure 55. Auxiliary DAC Structure
The control registers for the I and Q auxiliary DACs are
Register 0x42, Register 0x43, Register 0x46, and Register 0x47.
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參數(shù)描述
AD9146BCPZRL 功能描述:IC DAC 16BIT SRL DUAL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:*
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