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參數(shù)資料
| 型號： | AD9146BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/56頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SRL DUAL 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| 設(shè)置時(shí)間： | 20ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-WQ（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 1.23G |
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Data Sheet
AD9146
Rev. A | Page 49 of 56
INTERRUPT REQUEST OPERATION
The AD9146 provides an interrupt request output signal on
Pin 34 (IRQ) that can be used to notify an external host processor
of significant device events. Upon assertion of the interrupt, the
device should be queried to determine the precise event that
occurred. The IRQ pin is an open-drain, active low output. Pull
the IRQ pin high external to the device. This pin can be tied to
the interrupt pins of other devices with open-drain outputs to
wire-OR these pins together.
The event flags provide visibility into the device. These flags
are located in the two event flag registers, Register 0x06 and
Register 0x07. The behavior of each event flag is independently
selected in the interrupt enable registers, Register 0x04 and
Register 0x05. When the flag interrupt enable is active, the
event flag latches and triggers an external interrupt. When the
flag interrupt is disabled, the event flag monitors the source
signal, but the IRQ pin remains inactive.
Figure 68 shows the IRQ-related circuitry and how the event
flag signals propagate to the IRQ output. The INTERRUPT_
ENABLE signal represents one bit from the interrupt enable
register. The EVENT_FLAG_SOURCE signal represents one bit
from the event flag register. The EVENT_ FLAG_SOURCE
signal represents one of the device signals that can be monitored,
such as the PLL_LOCKED signal from the PLL phase detector
or the FIFO_WARNING_1 signal from the FIFO controller.
When an interrupt enable bit is set high, the corresponding event
flag bit reflects a positively tripped version of the EVENT_FLAG_
SOURCE signal; that is, the event flag bit is latched on the rising
edge of the EVENT_FLAG_SOURCE signal. This signal also
asserts the external IRQ pin.
When an interrupt enable bit is set low, the event flag bit reflects
the current status of the EVENT_FLAG_SOURCE signal, and
the event flag has no effect on the external IRQ pin.
The latched version of an event flag (the INTERRUPT_SOURCE
signal) can be cleared in two ways. The recommended way is by
writing 1 to the corresponding event flag bit. A hardware or soft-
ware reset also clears the INTERRUPT_SOURCE signal.
INTERRUPT SERVICE ROUTINE
Interrupt request management starts by selecting the set of
event flags that require host intervention or monitoring. The
events that require host action should be enabled so that the
host is notified when they occur. For events requiring host
intervention upon IRQ activation, run the following routine
to clear an interrupt request:
1. Read the status of the event flag bits that are being
monitored.
2. Set the interrupt enable bit low so that the unlatched
EVENT_FLAG_SOURCE signal can be monitored directly.
3. Perform any actions that may be required to clear the
EVENT_FLAG_SOURCE. In many cases, no specific
actions may be required.
4. Read the event flag to verify that the actions taken have
cleared the EVENT_FLAG_SOURCE.
5. Clear the interrupt by writing 1 to the event flag bit.
6. Set the interrupt enable bits of the events to be monitored.
Note that some EVENT_FLAG_SOURCE signals are latched
signals. These signals are cleared by writing to the correspond-
ing event flag bit. For more information about each event flag,
see Register 0x06 and Register 0x07 in Table 11.
INTERRUPT_ENABLE
EVENT_FLAG_SOURCE
DEVICE_RESET
EVENT_FLAG
INTERRUPT_
SOURCE
1
0
OTHER
INTERRUPT
SOURCES
IRQ
WRITE_1_TO_EVENT_FLAG
09691-
074
Figure 68. Simplified Schematic of IRQ Circuitry
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| AD9146BCPZRL | 功能描述:IC DAC 16BIT SRL DUAL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD9146-EBZ | 制造商:Analog Devices 功能描述:16 BIT DUAL SIGNAL PROC DAC EB - Boxed Product (Development Kits) |
| AD9146-M5375-EBZ | 功能描述:BOARD EVAL FOR AD9146 DAC RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9148 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter |
| AD9148ARUZ | 制造商:Analog Devices 功能描述:- Rail/Tube |
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