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參數(shù)資料
| 型號(hào)： | AD9146BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/56頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT SRL DUAL 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| 設(shè)置時(shí)間： | 20ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-WQ（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 1.23G |
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Data Sheet
AD9146
Rev. A | Page 29 of 56
I AND Q
DACS
32
32 BITS
÷ INT
DCI
DACCLK
DATA
I AND Q
DATA
PATHS
DATA
FORMAT
INPUT
LATCH
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
RESET
LOGIC
FRAME
SYNC
FIFO SOFT ALIGN REQUEST
REG 0x18[1]
DATA/FIFO RATE
REG 0x10[6]
FIFO PHASE OFFSET
REG 0x17[2:0]
RE
AD
P
O
IN
T
E
R
RE
S
E
T
WR
IT
E
P
OIN
T
E
R
RE
S
E
T
READ
POINTER
WRITE
POINTER
09
69
1-
03
9
Figure 32. Block Diagram of FIFO
Nominally, data is written to and read from the FIFO at the same
rate. This keeps the FIFO depth constant. If data is written to the
FIFO faster than data is read out, the FIFO depth increases. If
data is read out of the FIFO faster than data is written to it, the
FIFO depth decreases. For optimum timing margin, the FIFO
depth should be maintained near half full (a difference of 4
between the write pointer and read pointer values). The FIFO
depth represents the FIFO pipeline delay and is part of the
overall latency of the AD9146.
Resetting the FIFO
When the AD9146 is powered on, the FIFO depth is unknown.
To avoid a concurrent read and write to the same FIFO address
and to ensure a fixed pipeline delay, it is important to reset the
FIFO pointers to known states. The FIFO pointers can be initial-
ized in two ways: via a write sequence to the serial port or by
strobing the FRAME input.
There are two types of FIFO reset: a relative reset and an absolute
reset. A relative reset enforces a defined FIFO depth. An absolute
reset enforces a particular write pointer value when the reset is
initiated. A serial port initiated FIFO reset is always a relative
reset. A FRAME strobe initiated reset can be either a relative or
an absolute reset.
The operation of the FRAME initiated FIFO reset depends on
the synchronization mode chosen.
When synchronization is disabled or when it is configured
for data rate mode synchronization, the FRAME strobe
initiates a relative FIFO reset. The reference point of the
relative reset is the position of the read pointer.
When FIFO mode synchronization is chosen, the FRAME
strobe initiates an absolute FIFO reset.
For more information about the synchronization function, see
the Multichip Synchronization section.
A summary of the synchronization modes and the types of
FIFO reset used is provided in Table 13.
Table 13. Summary of FIFO Resets
FIFO Reset Signal
Synchronization Mode
Disabled
Data Rate
FIFO Reset
Serial Port
Relative
FRAME
Relative
Absolute
For a FRAME dependent FIFO reset to occur, an extended
FRAME pulse must be sent to the part for proper operation.
The extended FRAME pulse must be asserted high for an entire
I and Q DAC data sample load. This corresponds to four data
clock samples in byte mode and eight data clock samples in
nibble mode (see Figure 33 and Figure 34, respectively).
Q0LSB
I1MSB
I1LSB
Q1MSB
Q1LSB
I2MSB
I2LSB
Q2MSB
Q2LSB
DCI
DATA
[15:0]
EXTENDED
FRAME
09
691
-09
7
Figure 33. Timing Diagram for Extended Frame Pulse (Byte Mode)
Q0N0
I1N3
I1N2
I1N1
I1N0
Q1N3
Q1N2
Q1N1
Q1N0
I2N3
DCI
DATA
[15:0]
EXTENDED
FRAME
0
9691-
098
Figure 34. Timing Diagram for Extended Frame Pulse (Nibble Mode)
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| AD9146BCPZRL | 功能描述:IC DAC 16BIT SRL DUAL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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