參數(shù)資料
型號(hào)： AD14060LBF-4
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 48/48頁(yè)
文件大小： 0K
描述： IC DSP CMOS 32BIT 308CQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類(lèi)型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時(shí)鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 2MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 308-CBQFP
供應(yīng)商設(shè)備封裝： 308-CQFP（52x52）
包裝： 托盤(pán)
AD14060/AD14060L
Rev. B | Page 9 of 48
MEMORY WRITE—BUS MASTER
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the AD14060/AD14060L is the bus master accessing external memory space.
These switching characteristics also apply for bus master synchronous read/write timing (see the Synchronous Read/Write—Bus Master
section). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
Table 9. Specifications
5 V
3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements:
tDAAK
ACK Delay from Address, Selects1, 2
13.5 + 7 DT/8 + W
ns
tDSAK
ACK Delay from WR Low1
8 + DT/2 + W
ns
Switching Characteristics:
tDAWH
Address, Selects to WR
De-asserted2
16.5 + 15 DT/16 + W
ns
tDAWL
Address, Selects to WR Low2
2.5 + 3 DT/8
ns
tWW
WR Pulse Width
12 + 9 DT/16 + W
ns
tDDWH
Data Setup before WR High
6.5 + DT/2 + W
ns
tDWHA
Address Hold after WR De-asserted
0 + DT/16 + H
ns
tDATRWH
Data Disable after WR De-asserted3
0.5 + DT/16 + H
6.5 + DT/16 + H
0.5 + DT/16 + H
6.5 + DT/16 + H
ns
tWWR
WR High to WR, RD, DMAGx Low
8 + 7 DT/16 + H
ns
tDDWR
Data Disable before WR or RD Low
4.5 + 3 DT/8 + 1
ns
tWDE
WR Low to Data Enabled
1.5 + DT/16
ns
tSADADC
Address, Selects to ADRCLK High2
0.5 + DT/4
ns
W = number of wait states specified in WAIT register × tCK.
H = tCK, if an address hold cycle occurs, as specified in WAIT register; otherwise, H = 0.
I = tCK, if a bus idle cycle occurs, as specified in WAIT register; otherwise, I = 0.
1 ACK delay/setup: User must meet tDAAK, tDSAK, or synchronous specification, tSACKC.
2 For MSx, SW, BMS, the falling edge is referenced.
3 See the
section for the calculation of hold times given capacitive and dc loads.
System Hold Time Calculation Example
RD, DMAG
ACK
DATA
WR
ADDRESS
MSx, SW
BMS
ADRCLK
(OUT)
tDAWH
tDAAK
tDSAK
tWDE
tDDWH
tWWR
tDDWR
tDATRWH
tSADADC
tWW
tDAWL
tDWHA
00667-
017
Figure 8. Memory Write—Bus Master
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