參數(shù)資料
型號： AD14060LBF-4
廠商： Analog Devices Inc
文件頁數(shù)： 24/48頁
文件大?。?/td> 0K
描述： IC DSP CMOS 32BIT 308CQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 2MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 308-CBQFP
供應(yīng)商設(shè)備封裝： 308-CQFP（52x52）
包裝： 托盤
AD14060/AD14060L
Rev. B | Page 30 of 48
PIN FUNCTION DESCRIPTIONS
AD14060/AD14060L pin function descriptions are listed in
Table 22. Inputs identified as synchronous (S) must meet timing
requirements with respect to CLKIN (or with respect to TCK
for TMS, TDI). Inputs identified as asynchronous (A) can be
asserted asynchronously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to VDD or GND, except
for ADDR31-0, DATA47-0, FLAG2-0, SW, and inputs that have
internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx,
TCLKx, RCLKx, LxDAT3-0, LxCLK, LxACK, TMS, and TDI)—
these pins can be left floating. These pins have a logic-level hold
circuit that prevents the input from floating internally.
Table 22. Pin Function Descriptions
Pin
Type1
Function
ADDR31-0
I/O/T
External Bus Address (common to all SHARCs). The AD14060/AD14060L outputs addresses for external memory
and peripherals on these pins. In a multiprocessor system, the bus master outputs addresses for read/writes on the
internal memory or IOP registers of slave ADSP-2106xs. The AD14060/AD14060L inputs addresses when a host
processor or multiprocessing bus master is reading or writing the internal memory or IOP registers of internal
ADSP-21060s.
DATA47-0
I/O/T
External Bus Data (common to all SHARCs). The AD14060/AD14060L inputs and outputs data and instructions on
these pins. 32-bit single-precision floating-point data and 32-bit fixed-point data is transferred over Bits 47–16 of
the bus. 40-bit extended-precision floating-point data is transferred over Bits 47–48 of the bus. 16-bit short word
data is transferred over Bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over Bits 23–16. Pull-up
resistors on unused DATA pins are not necessary.
MS3-0
O/T
Memory Select Lines (common to all SHARCs). These lines are asserted (low) as chip selects for the corresponding
banks of external memory. Memory bank size must be defined in the individual ADSP-21060’s system control
registers (SYSCON). The MS3-0 lines are decoded memory address lines that change at the same time as the other
address lines. When no external memory access is occurring, the MS3-0 lines are inactive. They are active, however,
when a conditional memory access instruction is executed, whether or not the condition is true. MS0 can be used
with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a multiprocessing system, the MS3-0 lines
are output by the bus master.
RD
I/O/T
Memory Read Strobe (common to all SHARCs). This pin is asserted (low) when the AD14060/AD14060L reads from
external devices or when the internal memory of internal ADSP-2106xs is being accessed. External devices
(including other ADSP-2106xs) must assert RD to read from the AD14060/AD14060L’s internal memory. In a
multiprocessing system, RD is output by the bus master and is input by all other ADSP-2106xs.
WR
I/O/T
Memory Write Strobe (common to all SHARCs). This pin is asserted (low) when the AD14060/AD14060L writes to
external devices or when the internal memory of internal ADSP-2106xs is being accessed. External devices
(including other ADSP-2106xs) must assert WR to write to the AD14060/ AD14060L’s internal memory. In a
multiprocessing system, WR is output by the bus master and is input by all other ADSP-2106xs.
PAGE
O/T
DRAM Page Boundary. The AD14060/AD16060L asserts this pin to signal that an external DRAM page boundary has
been crossed. DRAM page size must be defined in the individual ADSP-21060’s memory control register (WAIT).
DRAM can be implemented only in external memory Bank 0. The PAGE signal can be activated only for Bank 0
accesses. In a multiprocessing system, PAGE is output by the bus master.
ADRCLK
O/T
Clock Output Reference (common to all SHARCs). In a multiprocessing system, ADRCLK is output by the bus master.
SW
I/O/T
Synchronous Write Select (common to all SHARCs). This signal is used to interface the AD14060/AD14060L to
synchronous memory devices (including other ADSP-2106xs). The AD14060/AD14060L asserts SW (low) to provide
an early indication of an impending write cycle, which can be aborted, if WR is not later asserted (for example, in a
conditional write instruction). In a multiprocessing system, SW is output by the bus master and is input by all other
ADSP-2106xs to determine if the multiprocessor memory access is a read or write. SW is asserted at the same time
as the address output. A host processor using synchronous writes must assert this pin when writing to the
AD14060/AD14060L.
ACK
I/O/S
Memory Acknowledge (common to all SHARCs). External devices can de-assert ACK (low) to add wait states to an
external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off comple-
tion of an external memory access. The AD14060/AD14060L de-asserts ACK, as an output, to add wait states to a
synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-2106x de-asserts the bus
master’s ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its
ACK pin that maintains the input at the level to which it was last driven.
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