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| 型號： | AD14060LBF-4 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CMOS 32BIT 308CQFP |
| 產(chǎn)品培訓模塊： | SHARC Processor Overview |
| 標準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | 主機接口，連接端口，串行端口 |
| 時鐘速率： | 40MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 2MB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 308-CBQFP |
| 供應(yīng)商設(shè)備封裝： | 308-CQFP（52x52） |
| 包裝： | 托盤 |
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AD14060/AD14060L
Rev. B | Page 10 of 48
SYNCHRONOUS READ/WRITE—BUS MASTER
Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave
ADSP 2106x in multiprocessor memory space. These synchronous switching characteristics are also valid during asynchronous memory
reads and writes (see the Memory Read—Bus Master and Memory Write—Bus Master sections).
When accessing a slave ADSP-2106x, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see the Synchronous Read/Write—Bus Slave section). The slave ADSP-2106x must also meet these bus master timing
requirements for data and acknowledge setup and hold times.
Table 10. Specifications
5 V
3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements:
tSSDATI
Data Setup before CLKIN
3 + DT/8
ns
tHSDATI
Data Hold after CLKIN
4 DT/8
ns
tDAAK
ACK Delay after Address, MSx, SW, BMS1, 2
13.5 + 7 DT/8 + W
ns
tSACKC
ACK Setup before CLKIN2
6.5 + DT/4
ns
tHACKC
ACK Hold after CLKIN
0.5 DT/4
ns
Switching Characteristics:
tDADRO
Address, MSx, BMS, SW, Delay after CLKIN1
8 DT/8
ns
tHADRO
Address, MSx, BMS, SW, Hold after CLKIN
1 DT/8
ns
tDPGC
PAGE Delay after CLKIN
9 + DT/8
17 + DT/8
9 + DT/8
17 + DT/8
ns
tDRDO
RD High Delay after CLKIN
2 DT/8
+5 DT/8
2 DT/8
+5 DT/8
ns
tDWRO
WR High Delay after CLKIN
3 3 DT/16
+5 3 DT/16
3 3 DT/16
+5 3 DT/16
ns
tDRWL
RD/WR Low Delay after CLKIN
8 + DT/4
13.5 + DT/4
8 + DT/4
13.5 + DT/4
ns
tSDDATO
Data Delay after CLKIN
20 + 5 DT/16
20.25 + 5 DT/16
ns
tDATTR
Data Disable after CLKIN3
0 DT/8
8 DT/8
0 DT/8
8 – DT/8
ns
tDADCCK
ADRCLK Delay after CLKIN
4 + DT/8
11 + DT/8
4 + DT/8
11 + DT/8
ns
tADRCK
ADRCLK Period
tCK
ns
tADRCKH
ADRCLK Width High
(tCK/2 2)
ns
tADRCKL
ADRCLK Width Low
(tCK/2 2)
ns
W = number of wait states specified in WAIT register × tCK.
1 For MSx, SW, BMS, the falling edge is referenced.
2 ACK delay/setup: User must meet tDAAK, tDSAK, or synchronous specification, tSACKC.
3 See the
section for the calculation of hold times given capacitive and dc loads.
System Hold Time Calculation Example
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