參數(shù)資料
型號(hào)： AD14060LBF-4
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP CMOS 32BIT 308CQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時(shí)鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 2MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 308-CBQFP
供應(yīng)商設(shè)備封裝： 308-CQFP（52x52）
包裝： 托盤(pán)
AD14060/AD14060L
Rev. B | Page 41 of 48
TOP VIEW
13
14
11
12
910
9
78
56
34
12
EMU
CLKIN (OPTIONAL)
TMS
TCK
TRST
TDI
TDO
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
00667-008
Table 24. JTAG Signals
Signal
Termination
TMS
Driven through 22 resistor (16 A to 3.2 A driver).
TCK
Driven at 10 MHz through 22 resistor (16 A to 3.2 A
driver).
TRST
Driven by open-drain driver1 (pulled up by on-chip
20 k resistor).
TDI
Driven by 16 A to 3.2 A driver.
TDO
One TTL load, no termination.
CLKIN
One TTL load, no termination (optional signal).
EMU
4.7 k pull-up resistor, one TTL load (open-drain
output from ADSP-2106x).
______________________________________
1 TRST is driven low until the emulator probe is turned on by the emulator
software (after the invocation command).
Connecting CLKIN to Pin 4 of the emulator header is optional.
The emulator uses CLKIN only when directed to perform
operations such as starting, stopping, and single-stepping
multiple ADSP-2106xs in a synchronous manner. If these
operations do not need to occur synchronously on the multiple
processors, tie Pin 4 of the emulator header to ground.
Figure 26. Target Board Connector for ADSP-2106x Emulator
(Jumpers in Place)
The 14-pin, 2-row pin-strip header is keyed at the Pin 3 loca-
tion; Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 inch × 0.1 inch. Pin strip headers are available
from vendors such as 3M, McKenzie, and Samtec.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the AD14060/
AD14060L and the CLKIN pin on the emulator header must be
minimal. If the skew is too large, synchronous operations might
be off by one cycle between processors. For synchronous multi-
processor operation, TCK, TMS, CLKIN, and EMU should be
treated as critical signals in terms of skew, and should be laid
out as short as possible on the board.
The BTMS, BTCK, BTRST, and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the other pins, as shown in
Figure 26. If you are not going to use the test access port for
board testing, tie BTRST to GND and tie or pull up BTCK to
VDD. The TRST pin must be asserted after power-up (through
BTRST on the connector) or held low for proper operation of
the AD14060/AD14060L. None of the Bxxx pins (Pins 5, 7, 9,
11) are connected on the emulator probe.
If TCK, TMS, and CLKIN are driving a large number of
ADSP-2106x’s (more than eight) in the system, treat them as a
clock tree using multiple drivers to minimize skew. (See the
ADSP-2106x User’s Manual for details).
If synchronous multiprocessor operations are not needed
(CLKIN is not connected), use appropriate parallel termination
on TCK and TMS. Note that TDI, TDO, EMU, and TRST are
not critical signals in terms of skew.
The JTAG signals are terminated on the emulator probe as
listed in Table 24.
Figure 27 shows JTAG scan path connections for the
multiprocessor system.
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