參數(shù)資料
型號(hào)： AD14060LBF-4
廠商： Analog Devices Inc
文件頁數(shù)： 23/48頁
文件大小： 0K
描述： IC DSP CMOS 32BIT 308CQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時(shí)鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 2MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 308-CBQFP
供應(yīng)商設(shè)備封裝： 308-CQFP（52x52）
包裝： 托盤
AD14060/AD14060L
Rev. B | Page 3 of 48
SPECIFICATIONS
Table 1. Recommended Operating Conditions
B Grade
K Grade
Parameter
Min
Max
Min
Max
Unit
VDD
Supply Voltage (5 V)
4.75
5.25
4.75
5.25
V
Supply Voltage (3.3 V)
3.15
3.6
3.15
3.6
V
TCASE
Case Operating Temperature
40
+100
0
+85
°C
ELECTRICAL CHARACTERISTICS (3.3 V, 5 V SUPPLY)
Table 2.
5 V
3.3 V
Parameter
Case
Temp
Test
Level
Test Condition
Min
Typ
Max
Min
Typ
Max
Unit
VIH1
High Level Input Voltage1
Full
I
@ VDD = max
2.0
VDD + 0.5
2.0
VDD + 0.5
V
VIH2
High Level Input Voltage2
Full
I
@ VDD = max
2.2
VDD + 0.5
2.2
VDD + 0.5
V
VIL
Low Level Input Voltage1, 2
Full
I
@ VDD = min
0.8
V
VOH
High Level Output Voltage3, 4
Full
I
@ VDD = min, IOH = 2.0 mA
4.1
2.4
V
VOL
Low Level Output Voltage3, 4
Full
I
@ VDD = min, IOL = 4.0 mA
0.4
V
IIH
High Level Input Current5, ,6 7
Full
I
@ VDD = max, VIN = VDD max
10
A
IIL
Low Level Input Current5
Full
I
@ VDD = max, VIN = 0 V
10
A
IILP
Low Level Input Current6
Full
I
@ VDD = max, VIN = 0 V
150
A
IILPX4
Low Level Input Current7
Full
I
@ VDD = max, VIN = 0 V
600
A
IOZH
Three-State Leakage Current8, , ,
Full
I
@ VDD = max, VIN = VDD max
10
A
IOZL
Three-State Leakage Current8, 12
Full
I
@ VDD = max, VIN = 0 V
10
A
IOZHP
Three-State Leakage Current12
Full
I
@ VDD = max, VIN = VDD max
350
A
IOZLC
Three-State Leakage Current13
Full
I
@ VDD = max, VIN = 0 V
1.5
mA
IOZLA
Three-State Leakage Current14
Full
I
@ VDD = max,
VIN = 1.5 V (5 V), 2 V (3.3 V)
350
A
IOZLAR
Three-State Leakage Current10
Full
I
@ VDD = max, VIN = 0 V
4.2
mA
IOZLS
Three-State Leakage Current9
Full
I
@ VDD = max, VIN = 0 V
150
A
IOZLSX4
Three-State Leakage Current11
Full
I
@ VDD = max, VIN = 0 V
600
A
IDDIN
Supply Current (Internal)15
Full
IV
tCK = 25 ns, VDD = max
1.4
2.92
1.0
2.2
A
IDDIDLE
Supply Current (Idle)16
Full
I
VDD = max
800
760
mA
CIN
Input Capacitance17, 18
25°C
V
15
pF
1 Applies to input and bidirectional pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, STBS, IRQy2-0, FLAGy0, FLAG1, FLAGy2, HBG, CSy, DMAR1, DMAR2, BR6-1, RPBA, CPAy, TFS0,
TFSy1, RFS0, RFSy1, LyxDAT3-0, LyxCLK, LyxACK, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, BMSA, BMSBCD, TMS, TDI, TCK, HBR, DR0, DRy1, TCLK0, TCLKy1, RCLK0,
RCLKy1.
2 Applies to input pins: CLKIN, RESET, TRST.
3 Applies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, TIMEXPy, HBG, REDY, DMAG1, DMAG2,
BR6-1, CPAy, DTO, DTy1, TCLK0, TCLKy1, RCLK0, RCLKy1, TFS0, TFSy1, RFS0, RFSy1, LyxDAT3-0, LyxCLK, LyxACK, BMSA, BMSBCD, TDO, EMU.
4 See the
section for typical drive current capabilities.
Output Drive Currents
5 Applies to input pins: STBS, IRQy2-0, HBR, CSy, DMAR1, DMAR2, RPBA, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, CLKIN, RESET, TCK.
6 Applies to input pins with internal pull-ups: DR0, DRy1, TDI.
7 Applies to bused input pins with internal pull-ups: TRST, TMS.
8 Applies to three-statable pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, REDY, HBG, DMAG1, DMAG2, BMSA, BMSBCD, TDO,
EMU. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-2106x is not requesting bus
mastership. HBG and EMU are not tested for leakage current.)
9 Applies to three-statable pins with internal pull-ups: DTy1, TCLKy1, RCLKy1.
10 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID2-0 = 001 and another
ADSP-2106x is not requesting bus mastership.)
11 Applies to bused three-statable pins with internal pull-ups: DT0, TCLK0, RCLK0.
12 Applies to three-statable pins with internal pull-downs: LyxDAT3-0, LyxCLK, LyxACK.
13 Applies to CPAy pin.
14 Applies to ACK pin, when the keeper latch is enabled.
15 Applies to VDD pins. Conditions of operation: each processor is executing radix-2 FFT butterfly with instruction in cache, one data operand is fetched from each
internal memory block, and one DMA transfer is occurring from/to internal memory at tCK = 25 ns.
16 Applies to VDD pins. Idle denotes AD14060/AD14060L state during execution of IDLE instruction.
17 Applies to all signal pins.
18 Guaranteed, but not tested.
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