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參數(shù)資料
| 型號(hào)： | 73S1209F-EB |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 95/123頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL 73S1209F DOC/CD CABLE |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | * |
| 嵌入式： | * |
| 已用 IC / 零件： | * |
| 主要屬性： | * |
| 次要屬性： | * |
| 已供物品： | 板，線纜，CD，電源 |
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DS_1209F_004
73S1209F Data Sheet
Rev. 1.2
73
PLL
ETU Divider
12 bits
FI Decoder
DIV
by
2
ETUCLK
CLK
DIV
by
2
SCLK
Pre-Scaler
6 bits
Pre-Scaler
6 bits
F/D Register
SCCLK(5:0)
SCSCLK(5:0)
MSCLK
MSCLKE
MCLK =
96MHz
FDReg(3:0)
FDReg(7:4)
9926
1/744
3.69M
1/13
7.38M
3.69M
7.38M
Defaults
in Italics
SCSel(3:2)
1/13
SYNC
CENTER
EDGE
Figure 17: Smart Card CLK and ETU Generation
There are two, two-byte FIFOs that are used to buffer transmit and receive data. During a T=0 processing,
if a parity error is detected by the 73S1209F during message reception, an error signal (BREAK) will be
generated to the smart card. The byte received will be discarded and the firmware notified of the error.
Break generation and receive byte dropping can be disabled under firmware control. During the
transmission of a byte, if an error signal (BREAK) is detected, the last byte is retransmitted again and the
firmware notified. Retransmission can be disabled by firmware. When a correct byte is received, an
interrupt is generated to the firmware, which then reads the byte from the receive FIFO. Receive overruns
are detected by the hardware and reported via an interrupt. During transmission of a message, the
firmware will write bytes into the transmit FIFO. The hardware will send them to the smart card. When the
last byte of a message has been written, the firmware will need to set the LASTTX bit in the STXCtl SFR.
This will cause the hardware to insert the CRC/LRC if in a T=1 protocol mode. CRC/LRC
generation/checking is only provided during T=1 processing. Firmware will need to instruct the smart
function to go into receive mode after this last transmit data byte if it expects a response from the smart
card. At the end of the smart card response, the firmware will put the interface back into transmit mode if
appropriate.
The hardware can check for the following card-related timeouts:
Character Waiting Time (CWT)
Block Waiting Time (BWT)
Initial Waiting Time (IWT)
The firmware will load the Wait Time registers with the appropriate value for the operating mode at the
appropriate time. Figure 18 shows the guard, block, wait and ATR time definitions. If a timeout occurs,
an interrupt will be generated and the firmware can take appropriate recovery steps. Support is provided
for adding additional guard times between characters using the Extra Guard Time register (EGT) and
between the last byte received by the 73S1209F and the first byte transmitted by the 73S1209F using the
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| 73S1209F-IM44 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
| 73S1209F-IM44 EB | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Eval Brd Eval Bd Doc Cd Cable |
| 73S1209F-IM68 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
| 73S1209F-IM68 EB | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Eval Brd Doc Cd Cable |
| 73S1210F | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Self-Contained Smart Card Reader with PINpad and Power Management |
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