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參數(shù)資料
| 型號： | 73S1209F-EB |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 93/123頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL 73S1209F DOC/CD CABLE |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | * |
| 嵌入式： | * |
| 已用 IC / 零件： | * |
| 主要屬性： | * |
| 次要屬性： | * |
| 已供物品： | 板，線纜，CD，電源 |
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DS_1209F_004
73S1209F Data Sheet
Rev. 1.2
71
1.7.13.2 Answer to Reset Processing
A card insertion event generates an interrupt to the firmware, which is then responsible for the
configuration of the electrical interface, the UART and activation of the card. The activation sequencer
goes through the power up sequence as defined in the ISO 7816-3 specification. An asynchronous
activation timing diagram is shown in Figure 15. After the card reset is de-asserted, the firmware instructs
the hardware to look for a TS byte that begins the ATR response. If a response is not provided within the
pre-programmed timeout period, an interrupt is generated and the firmware can then take appropriate
action, including instructing the 73S1209F to begin a deactivation sequence. Once commanded, the
deactivation sequencer goes through the power down sequence as defined in the ISO 7816-3
specification. If an ATR response is received, the hardware looks for a TS byte that determines
direct/inverse convention. The hardware handles the indirect convention conversion such that the
embedded firmware only receives direct convention. This feature can be disabled by firmware within
SByteCtl register. Parity checking and break generation is performed on the TS byte unless disabled by
firmware. If during the card session, a card removal, over-current or other error event is detected, the
hardware will automatically perform the deactivation sequence and then generate an interrupt to the
firmware. The firmware can then perform any other error handling required for proper system operation.
Smart card RST, I/O and CLK, C4, C8 shall be low before the end of the deactivation sequence. Figure
16 shows the timing for a deactivation sequence.
VCCSEL
bits
VCC
VCCOK bit
RSTCRD bit
RST
CLK
IO
t1
t2
t3
t4
t5
tto
See Note
ATR starts
t4
SELSC
bits
t1: SELSC.1 bit set (selects internal ICC interface) and a non-zero value in VCCSEL bits (calling for a
value of Vcc of 1.8, 3.0, or 5.0 volts) will begin the activation sequence. t1 is the time for Vcc to rise
to acceptable level, declared as Vcc OK (bit VCCOK gets set). This time depends on filter capacitor
value and card Icc load.
tto: The time allowed for Vcc to rise to Vcc OK status after setting of the VCCSEL bits. This time is
generated by the VCCTMR counter. If Vcc OK is not set, (bit VCCOK) at this time, a deactivation will
be initiated. VCCSEL bits are not automatically cleared. The firmware must clear the VCCSEL bits
before starting a new activation.
t2: Time from VCCTmr timeout and VCC OK to IO reception (high), typically 2-3 CLK cycles if
RDYST = 0. If RDYST = 1, t2 starts when VCCOK = 1.
t3: Time from IO = high to CLK start, typically 2-3 CLK cycles.
t4: Time allowed for start of CLK to de-assertion of RST. Programmable by RLength register.
t5: Time allowed for ATR timeout, set by the STSTO register.
Note: If the RSTCRD bit is set, RST is asserted (low). Upon clearing RSTCRD bit, RST will be
de-asserted after t4.
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相關(guān)代理商/技術(shù)參數(shù) |
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| 73S1209F-IM44 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
| 73S1209F-IM44 EB | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Eval Brd Eval Bd Doc Cd Cable |
| 73S1209F-IM68 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
| 73S1209F-IM68 EB | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Eval Brd Doc Cd Cable |
| 73S1210F | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Self-Contained Smart Card Reader with PINpad and Power Management |
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