2C write mode. C write " />
參數(shù)資料
型號： 73S1209F-EB
廠商： Maxim Integrated Products
文件頁數(shù)： 75/123頁
文件大?。?/td> 0K
描述： BOARD EVAL 73S1209F DOC/CD CABLE
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： *
嵌入式： *
已用 IC / 零件： *
主要屬性： *
次要屬性： *
已供物品： 板，線纜，CD，電源
DS_1209F_004
73S1209F Data Sheet
Rev. 1.2
55
Figure 9 shows the timing of the I
2C write mode.
C write mode.
1-7
8
9
10-17
18
ACK bit
STOP
condition
START
condition
1-7
8
9
10-17
18
ACK bit
STOP
condition
START
condition
SCL
SDA
LSB
MSB
LSB
MSB
Device Address
[7:0]
Write Data [7:0
I2C_Interrupt
Start I2C
(CSR bit1)
Transfer length
(CSR bit0)
1-7
8
9
10-17
18
ACK bit
STOP
condition
START
condition
SCL
SDA
LSB
MSB
LSB
MSB
Device Address
[7:0]
Write Data [7:0]
I2C_Interrupt
Start I2C
(CSR bit1)
Transfer length
(CSR bit0)
Secondary Write
Data [7:0]
ACK bit
19-26
27
LSB
MSB
Figure 9: I
2C Write Mode Operation
1.7.10.2 I2C Read Sequence
To read data on the I
2C Master Bus from a slave device, the 80515 has to program the following registers
in this sequence:
1. Write slave device address to Device Address register (DAR). The data contains 7 bits device
address and 1 bit of op-code. The op-code bit should be written with a 1.
2. Write control data to Control and Status register (CSR). Write a 1 to bit 1 to start I
2C Master Bus.
Also write a 1 to bit 0 if the Secondary Read Data register (SRDR) is to be captured from the I
2C
Slave device.
3. Wait for I
2C interrupt to be asserted. It indicates that the read operation on the I2C bus is done.
Refer to information about the INT6Ctl, IEN1 and IRCON registers for masking and flag operation.
4. Read data from the Read Data register (RDR).
5. Read data from Secondary Read Data register (SRDR) if bit 0 of Control and Status register (CSR) is
written with a 1.
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