參數(shù)資料
型號： 73S1209F-EB
廠商： Maxim Integrated Products
文件頁數(shù)： 44/123頁
文件大小： 0K
描述： BOARD EVAL 73S1209F DOC/CD CABLE
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： *
嵌入式： *
已用 IC / 零件： *
主要屬性： *
次要屬性： *
已供物品： 板，線纜，CD，電源
DS_1209F_004
73S1209F Data Sheet
Rev. 1.2
27
1.7.2 Power Control Modes
The 73S1209F contains circuitry to disable portions of the device and place it into lower power standby
modes. This is accomplished by either shutting off the power or disabling the clock going to the block.
The miscellaneous control registers MISCtl0, MISCtl1 and the Master Clock Control register (MCLKCtl)
provide control over the power modes. There is also a device power down mode that will stop the core,
clock subsystem and the peripherals connected to it. The PWRDN bit in MISCtl0 will setup the
73S1209F for power down and disable all clocks. The power down mode should only be initiated by
setting the PWRDN bit in the MISCtl0 register and not by manipulating individual control bits in various
VDDFAULT
Analog functions
(VCO, PLL,
reference and bias
circuits, etc.)
ANALOG
COMPARE
High Speed OSC
MISCtl0 - PWRDN
VDDFCtl - VDDFEN
ACOMP - CMPEN
MCLCKCtl - HOSEN
Smart Card Power
SCVCCCtl - SCPRDN
+
These are the registers and
the names of the control bits.
These are the
block references.
PWRDN Signal
Note: the PWRDN Signal is not the direct version of the PWRDN Bit. There are delays from assertion of the
PWRDN bit to the assertion of the PWRDN Signal (32 MPU clocks) Refer to the Power Down sequence diagram.
Flash Read Pulse
one-shot circuit
MISCtl1 - FRPEN
+
Figure 5: Power-Down Control
When the PWRDN bit is set, the clock subsystem will provide a delay of 32 MPUCLK cycles to allow the
program to set the STOP bit in the PCON register. This delay will enable the program to properly halt the
core before the analog circuits shut down (high speed oscillator, VCO/PLL, voltage reference and bias
circuitry, etc.). The PDMUX bit in SFR INT5Ctl should be set prior to setting the PWRDN bit in order to
configure the wake up interrupt logic. The power down mode is de-asserted by any of the interrupts
connected to external interrupts 0, 4 and 5 (external USR[0:7], smart card and Keypad). These interrupt
sources are OR’ed together and routed through some delay logic into INT0 to provide this functionality.
The interrupt will turn on the power to all sections that were shut off and start the clock subsystem. After
the clock subsystem clocks start running, the MPUCLK begins to clock a 512 count delay counter. When
the counter times out, the interrupt will then be active on INT0 and the program can resume. Figure 6
shows the detailed logic for waking up the 73S1209F from a power down state using these specific
interrupt sources. Figure 7 shows the timing associated with the power down mode.
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