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參數(shù)資料
| 型號： | 73S1209F-EB |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 27/123頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL 73S1209F DOC/CD CABLE |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | * |
| 嵌入式： | * |
| 已用 IC / 零件： | * |
| 主要屬性： | * |
| 次要屬性： | * |
| 已供物品： | 板，線纜，CD，電源 |
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73S1209F Data Sheet
DS_1209F_004
122
Rev. 1.2
Revision History
Revision
Date
Description
1.0
4/4/2007
First publication.
1.1
11/7/2007
In Table 1, added the Type column and the Equivalent Circuit references.
In Section 1.4, updated program security description to remove pre-boot
and 32-cycle references.
In Section 1.7.1, changed “Mcount is configured in the MCLKCtl register
must be bound between a value of 1 to 7. The possible crystal or external
clock are shown in Table 12.“ to “Mcount is configured in the MCLKCtl
register must be bound between a value of 1 to 7. The possible crystal or
external clock frequencies for getting MCLK = 96MHz are shown in Table
11.”
In the BRCON description, changed “If BSEL = 1, the baud rate is derived
using timer 1.” to “If BSEL = 0, the baud rate is derived using timer 1.”
In Section 1.7.12, removed the following from the emulator port
description: “The signals of the emulator port have weak pull-ups. Adding
resistor footprints for signals E_RST, E_TCLK and E_RXTX on the PCB is
recommended. If necessary, adding 10K
Ω pull-up resistors on E_TCLK
and E_RXTX and a 3K
Ω on E_RST will help the emulator operate
normally if a problem arises.”
In Ordering Information, removed the leaded part numbers.
1.2
12/16/2008
In Table 1, added more description to the SCL, SDA, PRES, PRESB,
VCC, VPC, SEC, TEST and VDD pins.
In Section 1.3.2, changed “FLSH_ERASE” to “ERASE” and
“FLSH_PGADR” to “PGADDR”. Added “The PGADDR register denotes
the page address for page erase. The page size is 512 (200h) bytes and
there are 128 pages within the flash memory. The PGADDR denotes the
upper seven bits of the flash memory address such that bit 7:1 of the
PGADDR corresponds to bit 15:9 of the flash memory address. Bit 0 of
the PGADDR is not used and is ignored.” In the description of the
PGADDR register, added “Note: the page address is shifted left by one bit
(see detailed description above).”
In Table 3, change “FLSH_PGADR” to “PGADDR”.
In Table 3, changed “FLSHCRL” to “FLSHCTL”.
In Table 3, added “Note: the page address is shifted left by one bit (see
detailed description above).” to the PGADDR description.
In Table 5, moved the TRIMPCtl bit description to FUSECtl and moved the
FUSECtl bit description to TRIMPCtl.
In Table 6, changed “PGADR” to “PGADDR”.
In Table 7, added PGADDR.
In Table 11, removed the Mcount 7 row.
In Section 1.7.13.5, deleted “The ETU clock is held in reset condition until
the activation sequence begins (either by VCCOK = 1 or VCCTMR
timeout) and will go high the ETU period thereafter.”
In Section 1.7.13.5 (number 3), deleted “If CLKOFF/SCLKOFF is high and
SYCKST is set=1(STXCtl, b7=1), Rlen=max will stop the clock at the
selected (CLKLVL or SCLKLVL) level.”
In Section 1.7.13.5, deleted number 9.
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| 73S1209F-IM44 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
| 73S1209F-IM44 EB | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Eval Brd Eval Bd Doc Cd Cable |
| 73S1209F-IM68 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
| 73S1209F-IM68 EB | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Eval Brd Doc Cd Cable |
| 73S1210F | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Self-Contained Smart Card Reader with PINpad and Power Management |
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